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SI4703-D30-GM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
Si4702/03-D30
Rev. 0.6 13
Audio Stereo Separation
3,9,12
25 — — dB
Mono/Stereo Switching Level
3,8,12
BLNDADJ = 10
10 dB stereo separation
—34—dBµVEMF
Audio Mono S/N
3,4,5,6,9
58 63 — dB
Audio Stereo S/N
3,5,6,8,14
BLNDADJ = 10 — 58 — dB
Audio THD
3,4,9,12
—0.10.5 %
De-emphasis Time Constant
8,13
DE = 0 70 75 80 µs
DE = 1 45 50 54 µs
Audio Common Mode Voltage
15
ENABLE = 1 0.65 0.8 0.9 V
Audio Common Mode Voltage
15
ENABLE = 0
AHIZEN = 1
—0.5xV
IO
—V
Audio Output Load Resistance
8,15
R
L
Single-ended 10 — — k
Audio Output Load Capacitance
8,15
C
L
Single-ended — — 50 pF
Seek/Tune Time
8,11
SPACE[1:0] = 0x, RCLK
tolerance = 200 ppm,
(x = 0 or 1)
——60ms/
channel
Powerup Time
8,16
From powerdown
(Write ENABLE bit to 1)
——110ms
RSSI Offset
17
Input levels of 8 and
60 dBµV at RF input
–3 — 3 dB
Table 8. FM Receiver Characteristics
1,2
(Continued)
(V
D
=V
A
= 2.7 to 5.5 V, V
IO
= 1.62 to 3.6 V, T
A
= –20 to 85 °C, 76–108 MHz)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Additional testing information is available in "AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure".
Volume = maximum for all tests.
2. Important Note: To ensure proper operation and FM receiver performance, follow the guidelines in “AN383: Si47xx
Antenna, Schematic, Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for
qualified customers.
3. F
MOD
= 1 kHz, 75 µs de-emphasis
4. MONO = 1, and L = R unless noted otherwise.
5. f = 22.5 kHz.
6. B
AF
= 300 Hz to 15 kHz, A-weighted.
7. Typical sensitivity with headphone matching network.
8. Guaranteed by characterization.
9. V
EMF
=1mV.
10. |f
2
– f
1
| > 1 MHz, f
0
=2xf
1
– f
2
. AGC is disabled by setting AGCD = 1. Refer to "6. Register Descriptions" on page 23.
11. The channel spacing is selected with the SPACE[1:0] bits. Refer to "6. Register Descriptions" on page 23. Seek/Tune
timing is guaranteed for 100 and 200 kHz channel spacing.
12. f = 75 kHz.
13. The de-emphasis time constant is selected with the DE bit. Refer to "6. Register Descriptions" on page 23.
14. RDS high-performance mode enabled RDSPRF 06h[9] = 1. Refer to 6. "Register Descriptions" on page 23.
15. At LOUT and ROUT pins.
16. Do not enable STC interrupts before the powerup time is complete. If STC interrupts are enabled before the powerup
time is complete, an interrupt will be generated within the powerup interval when the initial default tune operation is
complete. See "AN230: Si4700/01/02/03 Programming Guide" for more information.
17. Minimum and maximum at room temperature (25 °C).
Si4702/03-D30
14 Rev. 0.6
2. Typical Application Schematic
Notes:
1. Place C1 close to V
D
pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. Important Note: FM Receiver performance should adhere to the design guidelines described in “AN383: Si47xx
Antenna, Schematic, Layout, and Design Guidelines.” Failure to use these guidelines will negatively affect the
performance of the Si4702/03-D30, particularly in weak signal and noisy environments. Silicon Laboratories will evaluate
schematics and layouts for qualified customers.
5. Pin 2 connects to the antenna interface. Refer to AN383.
6. Place Si4702/03-D30 as close as possible to antenna jack and keep the FMIP trace as short as possible.
7. Refer to Si4702/03 Internal Crystal Oscillator Errata.
8. Refer to "AN299: External 32.768 kHz Crystal Oscillator”
3. Bill of Materials
Component(s) Value/Description Supplier(s)
C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata
U1 Si4702/03-D30 FM Radio Tuner Silicon Laboratories
C2, C3 Crystal load capacitors, 22 pF, ±5%, COG (Optional: for
crystal oscillator option)
Venkel
X1 32.768 kHz crystal (Optional: for crystal oscillator option) Epson
20
19
18
17
16
NC
FMIP
RFGND
GND
RST
GND
LOUT
ROUT
GND
VD
NC
GPIO1
GPIO2
GPIO3
VA
SEN
SCLK
SDIO
RCLK
VIO
SEN
SCLK
SDIO
1
2
3
4
5
15
14
13
12
11
6
7
8
9
10
RST
RCLK
C1
GND
PAD
LOUT
ROUT
VBATTERY
2.7 to 5.5 V
GPIO1
GPIO2
GPIO3
VIO
1.62 to 3.6 V
FMIP
RFGND
C2 C3
X1
RCLK
GPIO3
Optional: for crystal oscillator option
Si4702/03-D30
Rev. 0.6 15
4. Functional Description
Figure 7. Si4702/03-D30 FM Receiver Block Diagram
4.1. Overview
The Si4702/03-D30 extends Silicon Laboratories
Si4700/01 FM tuner family, and further increases the
ease and attractiveness of adding FM radio reception to
mobile devices through small size and board area,
minimum component count, flexible programmability,
and superior, proven performance. Si4702/03-D30
software is backwards compatible to existing Si4700/01
and Si4702/03-B16 FM Tuner designs. The
Si4702/03-D30 benefits from proven digital integration
and 100% CMOS process technology, resulting in a
completely integrated solution. It is the industry's
smallest footprint FM tuner IC requiring only 10 mm
2
board space and one external bypass capacitor.
The device offers significant programmability, and
caters to the subjective nature of FM listeners and
variable FM broadcast environments world-wide
through a simplified programming interface and mature
functionality.
The Si4703-D30 incorporates a digital processor for the
European Radio Data System (RDS) and the US Radio
Broadcast Data System (RBDS) including all required
symbol decoding, block synchronization, error
detection, and error correction functions.
RDS enables data such as station identification and
song name to be displayed to the user. The Si4703-D30
offers a detailed RDS view and a standard view,
allowing adopters to selectively choose granularity of
RDS status, data, and block errors. Si4703-D30
software is backwards compatible to the proven Si4701,
adopted by leading cell-phone and MP3 manufacturers
world-wide.
The Si4702/03-D30 is based on the superior, proven
performance of Silicon Laboratories' Si4700/01
architecture offering unmatched interference rejection
and leading sensitivity. The device uses the same
programming interface as the Si4701 and supports
multiple bus-modes. Power management is also
simplified with an integrated regulator allowing direct
connection to a 2.7 to 5.5 V battery.
The Si4702/03-D30 device’s high level of integration
and complete FM system production testing increases
quality to manufacturers, improves device yields, and
simplifies device manufacturing and final testing.
4.2. FM Receiver
The Si4702/03-D30’s patented digital low-IF
architecture reduces external components and
eliminates the need for factory adjustments. The receive
(RX) section integrates a low noise amplifier (LNA)
supporting the worldwide FM broadcast band (64 to
108 MHz). An automatic gain control (AGC) circuit
controls the gain of the LNA to optimize sensitivity and
rejection of strong interferers. For testing purposes, the
AGC can be disabled with the AGCD bit. Refer to
Section 6. "Register Descriptions" on page 23 for
additional programming and configuration information.
The Si4702/03-D30 architecture and antenna design
increases system performance. To ensure proper
performance and operation, designers should refer to
the guidelines in "AN383: Si47xx Antenna, Schematic,
VIO
CONTROLLER
I
ADC
Q
ADC
Si4702/03
DSP
FILTER
DEMOD
MPX
AUDIO
SCLK
SDIO
CONTROL
INTERFACE
SEN
DAC
DAC
ROUT
LOUT
0 / 90 LOW-IF
RSSI
TUNE
GPIO
AMPLIFIER
GPIO
RST
RFGND
LNA
FMIP
AFC
AGC
PGA
RCLK
REG
VA
VD
32.768 kHz
2.7 - 5.5 V
Headphone
Cable
RDS
(Si4703)
XTAL
OSC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

SI4703-D30-GM

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Buy SI4703-D30-GM
Manufacturer:
Silicon Labs
Description:
RF RCVR FM 76MHZ-108MHZ 20QFN
Lifecycle:
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