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NB3N853531EDTG

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2012
March, 2012 − Rev. 6
1 Publication Order Number:
NB3N853531E/D
NB3N853531E
3.3 V Xtal or
LVTTL/LVCMOS Input 2:1
MUX to 1:4 LVPECL Fanout
Buffer
Description
The NB3N853531E is a low skew 3.3 V supply 1:4 clock
distribution fanout buffer. An input MUX selects either a
Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by
using the CLK_SEL pin (HIGH for Crystal, LOW for Clock) with
LVCMOS / LVTTL levels.
The single ended CLK input is translated to four LVPECL Outputs.
Using the crystal input, the NB3N853531E can be a Clock Generator.
A CLK_EN pin can enable or disable the outputs synchronously to
eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable
outputs, LOW to disable outputs).
Features
• Four Differential 3.3 V LVPECL Outputs
• Selectable Crystal or LVCMOS/LVTTL CLOCK Inputs
• Up to 266 MHz Clock Operation
• Output to Output Skew: 30 ps (Max)
• Device to Device Skew 200 ps (Max)
• Propagation Delay 1.8 ns (Max)
• Operating Range: V
CC
= 3.3 ±5% V( 3.135 to 3.465 V)
• Additive Phase Jitter, RMS: 0.053 ps (Typ)
• Synchronous Clock Enable Control
• Industrial Temp. Range (−40°C to 85°C)
• Pb−Free TSSOP−20 Package
• Ambient Operating Temperature Range −40°C to +85°C
• These are Pb−Free Devices
Figure 1. Simplified Logic Diagram
OSC
Pullup
CLK_EN
Pulldown
CLK
XTAL_IN
XTAL_OUT
Pulldown
1
0
D
Q
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
CLK_SEL
MARKING
DIAGRAM
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
http://onsemi.com
(Note: Microdot may be in either location)
See detailed ordering and shipping information in the
package dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
TSSOP−20
DT SUFFIX
CASE 948E
NB3N
531E
ALYWG
G
NB3N853531E
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2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
Q0
V
CC
Q1
Q1
Q2
Q2
V
CC
Q3
Q3
V
EE
CLK_EN
CLK_SEL
nc
XTAL_IN
XTAL_OUT
nc
nc
V
CC
CLK
Figure 2. Pinout Diagram (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O
Open De-
fault
Description
1 V
EE
Negative (Ground) Power Supply pin must be externally connected to
power supply to guarantee proper operation.
2 CLK_EN LVCMOS /
LVTTL
Pullup Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
3 CLK_SEL LVCMOS /
LVTTL
Pulldown Clock Input Select (HIGH selects crystal, LOW selects CLK input)
4 CLK LVCMOS /
LVTTL
Pulldown Clock Input. Float open when unused.
5, 8, 9 nc No Connect
6 XTAL_IN Crystal Crystal Oscillator Input (used with pin 7). Float open when unused.
7 XTAL_OUT Crystal Crystal Oscillator Output (used with pin 6). Float open when unused.
10, 13, 18 V
CC
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
11, 14, 16,
19
Q[3:0] LVPECL Complement Differential Outputs (See AND8020 for termination)
12, 15, 17,
20
Q[3:0] LVPECL True Differential Outputs (See AND8020 for termination)
Table 2. FUNCTIONS
Inputs Outputs
CLK_EN CLK_SEL Input Function Output Function Qx Qx
0 0 CLK input selected Disabled LOW HIGH
0 1 Crystal Inputs Selected Disabled LOW HIGH
1 0 CLK input selected Enabled CLK0 Invert of
CLK1
1 1 Crystal Inputs Selected Enabled CLK1 Invert of
CLK1
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
NB3N853531E
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3
Figure 3. CLK_EN Timing Diagram
CLK
CLK_EN
EnabledDisabled
Q[0:3]
Q[0:3]
Table 3. ATTRIBUTES (Note 2)
Characteristics
Value
Internal Input Pullup Resistor
50 kW
Internal Input Pulldown Resistor
50 kW
C
in
Input Capacitance 4 pF
ESD Protection Human Body Model
Machine Model
> 2 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Level 1
Flammability Rating
Oxygen Index
UL 94 V−0 @ 0.125 in
28 to 34
Transistor Count 333 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 3)
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Supply Voltage 4.6 V
V
in
Input Voltage −0.5 v V
I
v VCC + 0.5 V
I
out
Output Current Continuous
Surge
50
100
mA
T
A
Operating Temperature Range, Industrial −40 to v +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
θ
JA
Thermal Resistance (Junction−to−Ambient)
0 lfpm Single−Layer
PCB (700 mm
2
,
2 oz)
128
°C/W
200 lfpm Multi−Layer
PCB (700 mm
2
,
2 oz)
94
θ
JC
Thermal Resistance (Junction−to−Case) (Note 4) TSSOP−20 23 to 41 °C/W
T
sol
Wave Solder 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
P1-P3P4-P6P7-P9

NB3N853531EDTG

Mfr. #:
Buy NB3N853531EDTG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer FAN-OUT BUFF W/CRYSL INPT
Lifecycle:
New from this manufacturer.
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