NB3N853531EDTG

NB3N853531E
http://onsemi.com
4
Table 5. CRYSTAL CHARACTERISTICS AND CONNECTIONS
Parameter Min Typ Max Unit
Mode of Oscillation Fundamental Parallel
Frequency 12 40 MHz
Equivalent Series Resistance (ESR) 50
W
Shunt Capacitance 7 pF
Drive Level 1 mW
Table 6. DC CHARACTERISTICS V
CC
= 3.3 ±5% V (3.135 to 3.465 V), V
EE
= 0 V, T
A
= 40°C to +85°C (Note 5)
Symbol Characteristic Min Typ Max Unit
I
EE
Power Supply Current 60 mA
V
IH
Input HIGH Voltage 2 V
CC
+ 0.3 V
V
IL
Input LOW Voltage 0.3 0.8 V
I
IH
Input High Current (V
CC
= 3.456 V) CLK, CLK_SEL = 3.456 V
CLK_EN = 3.456 V
150
5
mA
I
IL
Input LOW Current (V
CC
= 3.456 V) CLK, CLK_SEL = 3.456 V
CLK_EN = 3.456 V
5
150
mA
V
OH
Output HIGH Voltage V
CC
1.4 V
CC
0.9 V
V
OL
Output LOW Voltage V
CC
2.0 V
CC
1.7 V
VOUT
SWING
Output Voltage Swing (peaktopeak) 0.6 1.0 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs terminated 50 W to V
CC
2.0 V, see Figure 4.
Table 7. AC CHARACTERISTICS V
CC
= 3.3 ±5% V (3.135 to 3.465 V), V
EE
= 0 V, TA = 40°C to +85°C (Note 6)
Symbol Characteristic Min Typ Max Unit
F
MAX
Maximum Operating Frequency 0 266 MHz
t
PD
Propagation Delay (Notes 7 and 9) 1.1 1.8 ns
tSKEW
DC
Duty Cycle Skew same path similar conditions at 50 MHz (Notes 7, 8 and 9) 46 54 %
tSKEW
OO
Output to Output Skew Within A Device (Notes 7, 8 and 9) 30 ps
tSKEW
DD
Device to Device Skew similar path and conditions (Notes 7, 8 and 9) 200 ps
t
JIT
Additive Phase Noise Jitter (RMS) @ 155.52 MHz (Integrated from 12 kHz to
20 MHz) See Figure 6. (Note 9)
0.053 ps
t
r
/t
f
Output rise and fall times (20% and 80% points) (Note 9) 225 600 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50 W to V
CC
2.0 V, see Figure 4.
7. Measured under the same supply voltage, output loading, and input conditions.
8. Similar conditions.
9. Limits do not apply to overdriving XTAL_IN.
NB3N853531E
http://onsemi.com
5
Figure 4. Typical Test Setup and Termination for Evaluation. A split supply of V
CC
= 2.0 V and V
EE
= 1.3 +0.165 V
allows a convenient direct connection termination into typical oscilloscope 50 W to GND impedance modules.
For Application termination schemes see AND8020.
Z
o
= 50 W
Z
o
= 50 W
2 V
1.3 ± 0.165 V
50 W
50 W
Qx
Qx
LVPECL
V
EE
V
CC
Figure 5. AC Measurement Reference
V
CC
/2
V
CC
/2
Input
Output
20%
t
PD
t
PD
20%
80% 80%
t
R
t
F
Propagation Delay t
PD
Duty Cycle Skew t
SKEWDC
t
PW
t
Period
Output
tSKEW
DC
% +
ǒ
t
PW
ńt
Period
Ǔ
100
tSKEW
00
tSKEW
00
Input
CLKx
CLKy
OutputtoOutput Skew tSKEW
00
tSKEW
DD
tSKEW
DD
Input
Part #1
Part #2
Output
Output
DevicetoDevice Skew, tSKEW
DD
NB3N853531E
http://onsemi.com
6
Figure 6. For 155.52 MHz Carrier, the NB3N853531E Additive Phase Noise (dBc/Hz) verses SSB Offset Frequency
(Hz) Integrated Jitter from 12 kHz to 20 MHz (Upper Heavy Line) is 88.1 fs RMS. The E8663B Source Generator
Additive Phase Noise (Lower Light Line) is 70.1 fs RMS. Where t
JIT
= /(t
JIToutput
)
2
(t
JITinput
)
2
= 53 fs
NB3N853531E
Source Generator
Application Crystal Input Interface
Figure 7 shows the NB3N853531E device crystal
oscillator interface using a typical parallel resonant crystal.
A parallel crystal with loading capacitance C
L
= 18 pF could
use Series Load Caps C1 = 32 pF and C2 = 32 pF as nominal
values, after subtracting a typical 4 pF of stray cap per line.
The frequency accuracy and duty cycle skew can be fine
tuned by adjusting the C1 and C2 values. For example,
increasing the C1 and C2 values will reduce the operational
frequency. Note R1 is optional and may be 0 W.
Figure 7. NB3N853531E Crystal Oscillator Interface
*R1 is optional. Assuming 4 pF stray cap per pin.
32 pF
32 pF
C1
C2
XTAL_IN/CLK
XTAL_OUT
R1*
X1 18 pF
Parallel Resonant
Crystal

NB3N853531EDTG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer FAN-OUT BUFF W/CRYSL INPT
Lifecycle:
New from this manufacturer.
Delivery:
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