LT1768CGN#PBF Datasheet LT1768CGN#TRPBF, LT1768IGN#TRPBF, LT1768CGN#PBF | P13-P15

LT1768

APPLICATIONS INFORMATION

WUU

voltage and DIO lines can cause enough current flow to

fool the open lamp detection. In situations where coupling

can’t be avoided, resistors can be added from the DIO pins

to ground to increase the open lamp threshold. When

resistors from the DIO pins to ground are added, the

values for R

RMAX

and R

RMIN

may need to be increased

from their nominal values to compensate for the additional

current.

For single lamp operation, the lowside of the lamp should

be connected to both DIO pins, and the values of R

RMAX

and R

RMIN

increased to two times the values that would be

used in a dual lamp configuration. In single lamp mode all

fault detection will operate as in the dual lamp configura-

tion, but the open lamp threshold will double. If the

increase in the open lamp threshold is not acceptable, a

positive offset current can be added to reduce the open

lamp threshold by placing a resistor between the REF and

DIO pins (a 33k resistor will reduce the open lamp thresh-

old by approximately 100µA ((V

REF

–

DIO

)/33k). When

an offset current is added, the values for R

RMAX

and R

RMIN

may need to be increased from their nominal values to

compensate for the offset current.

VC Compensation

As previously mentioned a single capacitor on the VC pin

combines the error signal conversion, lamp current aver-

aging and frequency compensation. Careful consideration

should be given to the value of capacitance used. A large

value (1µF) will give excellent stability at high lamp cur-

rents but will result in degraded line regulation in PWM

mode. On the other hand , a small value (10nF) will give

excellent PWM response but might result in overshoot and

poor load regulation. The value chosen will depend on the

maximum load current and dimming range. After these

parameters are decided upon, the value of the VC capacitor

should be increased until the line regulation becomes

unacceptable. A typical value for the VC capacitor is

0.033µF. For further information on compensation please

refer to the references or consult the factory.

Current Sense Comparator

The LT1768 is a current mode PWM controller. Under

normal operating conditions the GATE is driven high at the

start of every oscillator cycle. The GATE is driven back low

when the current reaches a threshold level proportional to

the voltage on the VC pin. The GATE then remains low until

the start of the next oscillator cycle. The peak current is

thus proportional to the VC voltage and controlled on a

cycle by cycle basis. The peak switch current is normally

sensed by placing a sense resistor in the source lead of the

output MOSFET. This resistor converts the switch current

to a voltage that can be compared to a fraction of the VC

voltage [(V

– V

DIODE

)/30] . For normal conditions and a

GATE duty cycle below 50%, the switch current limit will

correspond to I

= 0.1/R

SENSE

. For GATE duty cycles

above 50% the switch current limit will be reduced

to approximately 90mV at 80% duty cycle to avoid

subharmonic oscillations associated with current mode

controllers.

When the lamp current is programmed to PWM mode, the

VC pin will slew between voltages that represent the

minimum and maximum PWM lamp currents. The slew

time affects the line regulation at low duty cycle, and

should be kept low by making the sense resistor as small

as possible. The lowest value of sense resistor is deter-

mined by switching transients and other noise due to

layout configurations. A good rule of thumb is to set the

sense resistor so that the voltage on the VC pin equals

2.5V when the PWM current is in maximum mode (V

PROG

= V

PWM

). Typical values of the sense resistor run in the

25mΩ to 50mΩ range for large displays, and can be

implemented with a copper trace on the PCB.

Since the maximum threshold at the SENSE pin is only

100mV, switching transients and other noise can prema-

turely trip the comparator. The LT1768 has a blanking

period of 100ns which prohibits premature switch turn

off, but further filtering the sense resistor voltage is

recommended. A simple RC filter is adequate for most

applications. (Figure 5.)

Figure 5. Sense Pin Filter

SENSE

GATE

LT1768

100Ω

2.2nF

0.025mΩ

1768 •F05

LT1768

up current source. The LT1768 thermal shutdown tem-

perature is set at 160°C. A buffered version of the internal

5V is present at the V

REF

pin and is capable of supplying up

to 10mA of current. Note that using any substantial

amount of current from the V

REF

pin will increase power

dissipation in the device, which will reduce the useful

operating ambient temperature range.

Supply and Input Voltage Sequencing

For most applications, where the SHDN pin is left floating,

and the voltages on the PWM and PROG pins are derived

from the V

REF

pin, the LT1768 will power-up and power-

down correctly when the voltage to the V

pin is applied

and removed. In applications where the voltage inputs for

the V

pin, SHDN pin, PWM pin, and the PROG pin

originate from different sources (power supply, micropro-

cessors etc.), care must be taken during power up/down

sequences. For proper operation during the power-up

sequence, the voltage on the following pins must be taken

from zero to their appropriate values in the following

order; V

pin, SHDN pin, PWM pin and PROG pin. For

proper operation during the power-down sequence, the

order must be reversed. For example, in the circuit of

Figure 1 where the SHDN pin is left floating, and the PWM

pin voltage is derived from a resistor divider to the V

REF

pin, the proper power-up sequence would be to take the

pin from zero to its value then apply either a voltage or

PWM signal to the PROG pin. The power-down sequence

for the circuit in Figure 1 would be to take the PROG pin

voltage to zero, then take the V

pin voltage to zero.If the

PROG voltage in the circuit of Figure 1 is present before the

supply voltage, proper power supply sequecing can be

achieved by implementing the circuit shown in Figure 7.

APPLICATIONS INFORMATION

WUU

1768 • G06

PGND

GATE

BAT 85

LT1768

GATE

The LT1768 has a single high current totem pole output

stage. This output stage is capable of driving up to ±1.5A

of output current. Cross-conduction current spikes in the

totem pole output have been eliminated. The GATE pin is

intended to drive an N-channel MOSFET switch. Rise and

fall times are typically 50ns with a 3000pF load. A clamp

is built into the device to prevent the GATE pin from rising

above 13V in order to protect the gate of the MOSFET

switch.

The GATE pin connects directly to the emitter of the upper

NPN drive transistor and the collector of the lower NPN

drive transistor in the totem pole. The collector of the lower

transistor, which is N-type silicon, forms a P-N junction

with the substrate of the device. This junction is reversed

biased during normal operation.

In some applications the parasitic LC of the external

MOSFET gate can ring and pull the GATE pin below

ground. If the GATE pin is pulled negative by more than a

diode drop the parasitic diode formed by the collector of

the GATE NPN and the substrate will turn on. This can

cause erratic operation of the device. In these cases a

Schottky clamp diode is recommended from the GATE pin

to ground. (Figure 6.)

Figure 6. Schottky Gate Clamp

49.9k

10k

10µF

0 TO 5V

1kHz PWM

VN2222LL

1768 F07

PROG

LT1768

Figure 7. Circuit Insures Proper Supply Sequencing When

Dimming Voltage Exists Before Main Power Supply

Reference

The internal reference of the LT1768 is a trimmed bandgap

reference. The reference is used to power the majority of

the LT1768 internal circuitry. The reference is inactive if

the LT1768 is in undervoltage lockout, shutdown mode, or

thermal shutdown. The undervoltage lockout is active

when V

is below 7.9V and the LT1768 is in shutdown

mode when the voltage on the SHDN pin is pulled below

1V. The SHDN pin has 200mV of hysteresis and a 7µA pull-

LT1768

APPLICATIONS INFORMATION

WUU

together with minimum trace between them. If space

constraints prohibit the transformer T1 placement next to

C1, local bypassing (C2) for the center tap of transformer

T1 should be used.

Special attention is also required for the layout of the high

voltage section to avoid any unpleasant surprises. Please

refer to the references for an extensive discussion on high

voltage layout techniques.

Applications Support

Linear Technology invests an enormous amount of time,

resources, and technical expertise in understanding, de-

signing and evaluating backlight solutions for systems

designers. The design of an efficient and compact back-

light system is a study of compromise in a transduced

electronic system. Every aspect of the design is interre-

lated and any design change requires complete re-evalu-

ation for all other critical design parameters. Linear

Technology has engineered one of the most complete test

and evaluation setups for backlight designs and under-

stands the issues and trade-offs in achieving a compact,

efficient and economical customer solution. Linear Tech-

nology welcomes the opportunity to discuss, design,

evaluate, and optimize any backlight system with a cus-

tomer. For further information on backlight designs, con-

sult the references below.

References

1. Williams, Jim. November 1995. A Fourth Generation of

LCD Backlight Technology. Linear Technology Corpora-

tion, Application Note 65.

1768 F08

*OPTIONAL

BOLD LINES INDICATE

HIGH CURRENT PATHS

LT1768

GATE

PGND

SENSE

Figure 8

Supply Bypass and Layout Considerations

Proper supply bypassing and layout techniques must be

used to insure proper regulation, avoid display flicker, and

insure long term reliability.

Figure 8 shows the application’s critical high current paths

in thick lines. Ideally, all components in the high current

path should be placed as close as possible and connected

with short thick traces. The most critical consideration is

that T1’s center tap, the Schottky diode D1, LT1768’s V

pin, and a low ESR capacitor (C1) be connected directly

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LT1768CGN#PBF

Mfr. #:

Buy LT1768CGN#PBF

Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators Hi Pwr CCFL Cntr for Wide Dimming Rng &

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

LT1768CGN#PBF

LT1768CGN#PBF

Products related to this Datasheet