LT1768
7
provides lamp current averaging and single pole loop
compensation.
AGND (Pin 6): The AGND pin is the low current analog
ground. It is the negative sense terminal for the internal
reference and current sense amplifier. Connect critical
external components that terminate to ground directly to
this pin for best performance.
C
T
(Pin 7): The value of capacitance on the C
T
pin deter-
mines the PWM modulation frequency. The transfer func-
tion of capacitance to frequency equals 22Hz/C
T
(µF). The
frequency present on the C
T
pin also determines the
maximum time allowed for lamp fault conditions. If the
current in either DIO1 or DIO2 is less than 125µA for a
minimum of 1 PWM period, the FAULT pin is activated and
the maximum allowable lamp current is reduced by ap-
proximately 50%. If the current in both DIO1 and DIO2 is
absent for a minimum of 1 PWM period, and the VC pin is
clamped at 3.7V, the FAULT pin is activated and the gate
drive of the part is internally latched off. The latch can be
cleared by setting the PROG voltage to zero or placing the
LT1768 in shutdown mode.
PROG (Pin 8): The PROG pin controls the lamp current by
converting a DC input voltage range of 0V to 5V to source
current into the VC pin. The transfer function from pro-
gramming voltage to VC current is illustrated in the follow-
ing table.
PROG (V) VC SOURCE CURRENT (µA)
V
PROG
< 0.5 0
0.5 < V
PROG
< 1.0 I
RMIN
1.0 < V
PROG
< V
PWM
PWM Mode*
V
CT
> V
PROG
I
RMIN
V
CT
< V
PROG
5 • I
RMAX
• ( V
PWM
– 1V)/ 3V
V
PROG
> 4.0 5 • I
RMAX
*PWM Duty Cycle = [1 – (V
PWM
– V
PROG
)/(V
PWM
– 1V)] • 100%
PWM (Pin 9): The PWM pin controls the percentage of the
PROG range between 1V and 4V that is to be pulse width
modulated. The percentage is defined by [(V
PWM
-1)/ 3] •
100%. The minimum and maximum percentages are 25%
(1.75V) and 100% (4V) respectively. Taking the PWM pin
above the 4V maximum will cause significant PWM input
current to flow. (See PWM Input Current vs Voltage curve
in Typical Performance Characteristics).
PIN FUNCTIONS
UUU
PGND (Pin 1): The PGND pin is the high current ground
path. High switching current transients and lamp current
flow through the PGND pin.
DIO1/DIO2 (Pins 3/2): Each DIO pin is the common
connection between the cathode and anode of two internal
diodes. The remaining terminals of the diodes are con-
nected to PGND. In a typical application, the DIO1/2 pins
are connected to the low voltage side of the lamps.
Bidirectional lamp current flows into the DIO1/2 pins and
their diodes conduct alternately on the half cycles. The
diode that conducts on the negative cycle has a percentage
of its current diverted into the VC pin. This current nulls
against the programming current specified by the PROG
and PWM pins. A single capacitor on the VC pin provides
both stable loop compensation and an averaging function
to the half wave-rectified lamp current. The
diode that
conducts on the positive cycle is used to detect open lamp
conditions. If the current in either of the DIO pins on the
positive cycle is less than 125µA for a minimum of 1 PWM
cycle, then the FAULT pin will be activated and the maxi-
mum source current into the VC pin will be reduced by
approximately 50%. If the current in both of the DIO pins
on the positive cycle is less than 125µA, and the VC pin hits
its clamp value (indicating either an open lamp or lamp
lowside short to ground fault condition) for a minimum of
1 PWM cycle, the gate drive will be latched off. The latch
can be cleared by setting the PROG voltage to zero or
placing the LT1768 in shutdown mode.
SENSE (Pin 4): The SENSE pin is the input to the current
sense comparator. The threshold of the comparator is a
function of the voltage on the VC pin and the switch duty
cycle. The maximum threshold is set at 100mV for duty
cycle less than 50% which corresponds to approximately
3.7V on the VC pin. The SENSE pin has a bias current of
25µA, which flows out of the pin.
VC (Pin 5): The VC pin is the summing junction for the
programming current and the half wave rectified lamp
current and is also an input to the current sense compara-
tor . A fraction of the voltage on the VC pin is compared to
the voltage on the SENSE pin (switch current) for switch
turnoff. During normal operation the VC pin sits between
0.7V (zero switch current) and 3.7V (maximum switch
current). A single capacitor between VC and AGND
LT1768
8
PIN FUNCTIONS
UUU
R
MAX
(Pin 10): The R
MAX
pin outputs a regulated voltage
of 1.25V that is to be loaded with an external resistor. The
current through the external resistor sets the maximum
lamp current. Maximum lamp current in a dual lamp
application will be approximately equal to 100 times I
RMAX
when the voltage on the PROG pin is greater than 4V. The
value of R
RMAX
must be greater than 5K and less than
[R
RMIN
• 2.5 • (V
PWM–1
/3)] for proper PWM operation.
R
MIN
(Pin 11): The R
MIN
pin outputs a regulated voltage of
1.26V that is to be loaded with an external resistor. The
current through the external resistor sets the minimum
lamp current. Minimum lamp current in a dual lamp
application will be approximately 10 times the value of
I
RMIN
when the voltage on the PROG pin is between 0.5V
and 1V. To set the minimum current to zero (I
RMIN
= 0µA)
for maximum dimming range, connect the R
MIN
pin to the
V
REG
pin. The value of R
RMIN
(R
RMIN
= when R
MIN
is
connected to V
REG
) must be greater than the value of
R
RMAX
/[0.4 • (V
PWM–1
)/3] for proper PWM operation.
SHDN (Pin 12): The SHDN pin controls the operation of
the LT1768. Pulling the SHDN pin above 1.26V or leaving
the pin open will result in normal operation of the LT1768.
Pulling the SHDN pin below 1V causes a complete shut-
down of the LT1768 which results in a typical quiescent
current of 65µA. The SHDN pin has an internal 7µA pull-up
source to V
IN
and 200mV of voltage hysteresis.
FAULT (Pin 13): The FAULT pin is an open collector output
with a sink capability of 1mA that is activated when lamp
current falls below 125µA in either DIO1 or DIO2 for at least
1 full PWM cycle.
V
REF
(Pin 14): The V
REF
pin is a regulated 5V output that is
derived from the V
IN
pin. The regulated voltage provides up
to 10mA of current to power external circuitry. During
undervoltage lockout, shutdown mode or thermal
shutdown, drive to the V
REF
pin will be disabled.
V
IN
(Pin 15): The V
IN
pin is the voltage supply pin for the
LT1768. For normal operation, the V
IN
pin must be above an
undervoltage lockout of 7.9V and below a maximum of 24V.
GATE (Pin 16): The GATE pin is the output of a NPN high
current output stage used to drive the gate of an external
MOSFET. It has a dynamic source and sink capability of
1.5A. During normal operation, the GATE pin is driven high
at the beginning of each oscillator period and then low
when the appropriate current in the switch is reached. The
GATE pin has a minimum on time of 125ns and a maximum
duty cycle of 93% at a frequency of 350kHz. For input
voltages less than 13V the gate will be driven to within 2V
of V
IN
. For input voltages greater than 13V the gate pin high
level will be clamped at a typical voltage of 12.5V.
LT1768
9
BLOCK DIAGRA
W
Figure 2. LT1768 Block Diagram
INTRODUCTION
The current trend in desktop monitor design is to migrate
the LCD (liquid crystal display) technology used in laptops
and instruments to the popular desktop display sizes. As
LCD size increases uniform backlighting requires mul-
tiple high power lamps. In addition, the lamps must have
a dimming range and lifetime expectancy comparable to
previous generations of desktop displays. Cold cathode
fluorescent lamps (CCFLs) provide the highest available
efficiency for backlighting LCD displays. The CCFL re-
quires a high voltage supply for operation. Typically, over
1000 volts is required to initiate CCFL operation, with
sustaining voltages from 200V to 800V. A CCFL can
operate from DC, but migration effects damage the CCFL
and shorten its lifetime. To achieve maximum life CCFL
drive should be sinusoidal, contain zero DC component,
and not exceed the CCFL manufacturers minimum and
maximum operating current ratings. Low crest factor
APPLICATIONS INFORMATION
WUU
U
sinusoidal CCFL drive also maximizes current to light
conversion, reduces display flicker, and minimizes EMI
and RF emissions. The LT1768 high power CCFL control-
ler, with its Multimode Dimming, provides the necessary
lamp drive to enable a wide dimming range while main-
taining lamp lifetime in multiple lamp CCFL applications.
BASIC OPERATION
Referring to the circuit in Figure 1, CCFL current is con-
trolled by a DC voltage on the PROG pin of the LT1768. The
DC voltage on the PROG pin feeds the LT1768’s Multimode
Dimming block and is converted to source current into the
VC pin. As the VC pin voltage rises, the LT1768’s GATE pin
is pulse width modulated at 350kHz. The GATE pulse width
is determined on a cycle by cycle basis by the voltage on
the SENSE pin (L1’s current multiplied by SENSE resistor
R5) exceeding a predetermined voltage set by the VC pin.
I
RMAX
I
RMIN
0
1V 4V
1.25V
1.26V
SLOPE
OSC
1V
V
PWM
PWM
VC
V
REF
R
MIN
R
MAX
V
IN
C
T
FAULT
SHDN
PROG
AGND
DI01 DIO2
GATE
SENSE
PGND
12
14
15
10
11
9
8
7
6
5
3
2
16
13
4
1
CONTROLMODE
I
VC
V
CCLAMP
FAULT
MULTI-MODE
DIMMING BLOCK
PWM PERIOD
UNDERVOLTAGE
LOCKOUT
THERMAL
SHUTDOWN
V
REF
(I
DIO1
+ I
DIO2
)
GAIN
I
VC
I
DIO2
< 125µA
I
DIO1
< 125µA
SW
BLANK
V
IN
GATE
S
Q
R
1768 BD

LT1768CGN#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Pwr CCFL Cntr for Wide Dimming Rng &
Lifecycle:
New from this manufacturer.
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