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AD676JDZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD676
REV. A
–9–
CONTINUOUS CONVERSION
For maximum throughput rate, the AD676 can be operated in a
continuous convert mode (see Figure 2b). This is accomplished
by utilizing the fact that SAMPLE will no longer be ignored af-
ter BUSY goes LOW, so an acquisition may be initiated even
during the HIGH time of the 17th CLK pulse for maximum
throughput rate while enabling full settling of the sample/hold
circuitry. If SAMPLE is already HIGH when BUSY goes LOW
at the end of a conversion, then an acquisition is immediately
initiated and t
S
and t
C
start from that time. Data from the previ-
ous conversion may be latched up to t
SD
before BUSY goes
LOW or t
OD
after the rising edge of the 17th clock pulse. How-
ever, it is preferred that latching occur on or after the falling
edge of BUSY.
Care must he taken to adhere to the minimum/maximum timing
requirements in order to preserve conversion accuracy.
GENERAL CONVERSION GUIDELINES
During signal acquisition and conversion, care should be taken
with the logic inputs to avoid digital feedthrough noise. It is pos-
sible to run CLK continuously, even during the sample period.
However, CLK edges during the sampling period, and especially
when SAMPLE goes LOW, may inject noise into the sampling
process. The AD676 is tested with no CLK cycles during the
sampling period. The BUSY signal can be used to prevent the
clock from running during acquisition, as illustrated in Figure 3.
In this circuit BUSY is used to reset the circuitry which divides
the system clock down to provide the AD676 CLK. This serves
to interrupt the clock until after the input signal has been ac-
quired, which has occurred when BUSY goes HIGH. When the
conversion is completed and BUSY goes LOW, the circuit in
Figure 3 truncates the 17th CLK pulse width which is tolerable
because only its rising edge is critical.
5
2 10
7
1
7
12
9
4
11
12.288MHz
SYSTEM
CLOCK
CLK
74HC175
2D
1Q
CLR
3D
2Q3Q
1D
BUSY
CLK
AD676
9
SAMPLE
2
8
9
12
6
13
1
1QD
74HC393
1CLR
2CLR
2QD
2QC
1CLK
2CLK
Figure 3.
Figure 3 also illustrates the use of a counter (74HC393) to de-
rive the AD676 SAMPLE command from the system clock
when a continuous convert mode is desirable. Pin 9 (2QC) pro-
vides a 96 kHz sample rate for the AD676 when used with a
12.288 MHz system clock. Alternately, Pin 8 (2QD) could be
used for a 48 kHz rate.
If a continuous clock is used, then the user must avoid CLK
edges at the instant of disconnecting V
IN
which occurs at the
falling edge of SAMPLE (see t
SC
specification). The duty cycle
of CLK may vary, but both the HIGH (t
CH
) and LOW (t
CL
)
phases must conform to those shown in the timing specifica-
tions. The internal comparator makes its decisions on the rising
edge of CLK. To avoid a negative edge transition disturbing the
comparator’s settling, t
CL
should be at least half the value of t
CLK
.
To also avoid transitions disturbing the internal comparator’s
settling, it is not recommended that the SAMPLE pin change
state toward the end of a CLK cycle.
During a conversion, internal dc error terms such as comparator
voltage offset are sampled, stored on internal capacitors and
used to correct for their corresponding errors when needed. Be-
cause these voltages are stored on capacitors, they are subject to
leakage decay and so require refreshing. For this reason there is
a maximum conversion time t
C
(1000 µs). From the time
SAMPLE goes HIGH to the completion of the 17th CLK pulse,
no more than 1000 µs should elapse for specified performance.
However, there is no restriction to the maximum time between
conversions.
Output coding for the AD676 is twos complement, as shown in
Table I. By inverting the MSB, the coding can be converted to
offset binary. The AD676 is designed to limit output coding in
the event of out-of-range inputs.
Table I. Output Coding
V
IN
Output Code
>Full Scale 011 . . . 11
Full Scale 011 . . . 11
Full Scale – 1 LSB 011 . . . 10
Midscale + 1 LSB 000 . . . 01
Midscale 000 . . . 00
Midscale – 1 LSB 111 . . . 11
–Full Scale + 1 LSB 100 . . . 01
–Full Scale 100 . . . 00
<–Full Scale 100 . . . 00
AD676
REV. A
–10–
POWER SUPPLIES AND DECOUPLING
The AD676 has three power supply input pins. V
CC
and V
EE
provide the supply voltages to operate the analog portions of the
AD676 including the ADC and sample-hold amplifier (SHA).
V
DD
provides the supply voltage which operates the digital por-
tions of the AD676 including the data output buffers and the
autocalibration controller.
As with most high performance linear circuits, changes in the
power supplies can produce undesired changes in the perfor-
mance of the circuit. Optimally, well regulated power supplies
with less than 1% ripple should be selected. The ac output im-
pedance of a power supply is a complex function of frequency,
and in general will increase with frequency. In other words, high
frequency switching such as that encountered with digital cir-
cuitry requires fast transient currents which most power supplies
cannot adequately provide. This results in voltage spikes on the
supplies. If these spikes exceed the ±5% tolerance of the ±12 V
supplies or the ±10% limits of the +5 V supply, ADC perfor-
mance will degrade. Additionally, spikes at frequencies higher
than 100 kHz will also degrade performance. To compensate for
the finite ac output impedance of the supplies, it is necessary to
store “reserves” of charge in bypass capacitors. These capacitors
can effectively lower the ac impedance presented to the AD676
power inputs which in turn will significantly reduce the magni-
tude of the voltage spikes. For bypassing to be effective, certain
guidelines should be followed. Decoupling capacitors, typically
0.1 µF, should be placed as closely as possible to each power
supply pin of the AD676. It is essential that these capacitors be
placed physically close to the IC to minimize the inductance of
the PCB trace between the capacitor and the supply pin. The
logic supply (V
DD
) should be decoupled to digital common and
the analog supplies (Vcc and V
EE
) to analog common. The ref-
erence input is also considered as a power supply pin in this re-
gard and the same decoupling procedures apply. These points
are displayed in Figure 4.
+5V
12V –12V
SYSTEM
ANALOG
COMMON
SYSTEM
DIGITAL
COMMON
AGND
DGND
AD676
17
121311
18
EE
V
CC
V
11
V
REF
V
DD
0.1µF
0.1µF
0.1µF
0.1µF
Figure 4. Grounding and Decoupling the AD676
Additionally, it is beneficial to have large capacitors (>47 µF)
located at the point where the power connects to the PCB with
10 µF capacitors located in the vicinity of the ADC to further
reduce low frequency ripple. In systems that will be subjected to
particularly harsh environmental noise, additional decoupling
may be necessary. RC-filtering on each power supply combined
with dedicated voltage regulation can substantially decrease
power supply ripple effects (this is further detailed in Figure 7).
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is a significant issue.
A 1.22 mA current through a 0.5 Ω trace will develop a voltage
drop of 0.6 mV, which is 4 LSBs at the 16-bit level for a 10 V
full-scale span. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital
signals.
Analog and digital signals should not share a common return
path. Each signal should have an appropriate analog or digital
return routed close to it. Using this approach, signal loops en-
close a small area, minimizing the inductive coupling of noise.
Wide PC tracks, large gauge wire, and ground planes are highly
recommended to provide low impedance signal paths. Separate
analog and digital ground planes are also desirable, with a single
interconnection point at the AD676 to minimize interference
between analog and digital circuitry. Analog signals should be
routed as far as possible from digital signals and should cross
them, if at all, only at right angles. A solid analog ground plane
around the AD676 will isolate it from large switching ground
currents. For these reasons, the use of wire wrap circuit con-
struction will not provide adequate performance; careful printed
circuit board construction is preferred.
GROUNDING
The AD676 has three grounding pins, designated ANALOG
GROUND (AGND), DIGITAL GROUND (DGND) and
ANALOG GROUND SENSE (AGND SENSE). The analog
ground pin is the “high quality” ground reference point for the
device, and should be connected to the analog common point in
the system.
AGND SENSE is intended to be connected to the input signal
ground reference point. This allows for slight differences in level
between the analog ground point in the system and the input
signal ground point. However no more than 100 mV is recom-
mended between the AGND and the AGND SENSE pins for
specified performance.
AD676
REV. A
–11–
Using AGND SENSE to remotely sense the ground potential of
the signal source can be useful if the signal has to be carried
some distance to the A/D converter. Since all IC ground cur-
rents have to return to the power supply and no ground leads
are free from resistance and inductance, there are always some
voltage differences from one ground point in a system to
another.
Over distance this voltage difference can easily amount to sev-
eral LSBs (in a 10 V input span, 16-bit system each LSB is
about 0.15 mV). This would directly corrupt the A/D input sig-
nal if the A/D measures its input with respect to power ground
(AGND) as shown in Figure 5a. To solve this problem the
AD676 offers an AGND SENSE pin. Figure 5b shows how the
AGND SENSE can be used to eliminate the problem in Figure
5a. Figure 5b also shows how the signal wires should be
shielded in a noisy environment to avoid capacitive coupling. If
inductive (magnetic) coupling is expected to be dominant such
as where motors are present, twisted-pair wires should be used
instead.
The digital ground pin is the reference point for all of the digital
signals that operate the AD676. This pin should be connected
to the digital common point in the system. As Figure 4 illus-
trated, the analog and digital grounds should be connected to-
gether at one point in the system, preferably at the AD676.
V
IN
AGND
SOURCE
V
S
GROUND LEAD
I
GROUND
> 0
TO POWER
SUPPLY GND
AD676
∆V
Figure 5a. Input to the A/D Is Corrupted by IR Drop in
Ground Leads: V
IN
= V
S
+
∆
V
V
IN
AGND
SENSE
AGND
SOURCE
V
S
SHIELDED CABLE
GROUND LEAD
I
GROUND
> 0
TO POWER
SUPPLY GND
AD676
Figure 5b. AGND SENSE Eliminates the Problem in
Figure 5a.
VOLTAGE REFERENCE
The AD676 requires the use of an external voltage reference.
The input voltage range is determined by the value of the refer-
ence voltage; in general, a reference voltage of n volts allows an
input range of ±n volts. The AD676 is specified for both 10 V
and 5.0 V references. A 10 V reference will typically require
support circuitry operated from ±15 V supplies; a 5.0 V refer-
ence may be used with ±12 V supplies. Signal-to-noise perfor-
mance is increased proportionately with input signal range. In
the presence of a fixed amount of system noise, increasing the
LSB size (which results from increasing the reference voltage)
will increase the effective S/(N+D) performance. Figure 12
illustrates S/(N+D) as a function of reference voltage. In
contrast, INL will be optimal at lower reference voltage values
(such as 5 V) due to capacitor nonlinearity at higher voltage
values.
During a conversion, the switched capacitor array of the AD676
presents a dynamically changing current load at the voltage ref-
erence as the successive-approximation algorithm cycles through
various choices of capacitor weighting. (See the following sec-
tion “Analog Input” for a detailed discussion of the V
REF
input
characteristics.) The output impedance of the reference circuitry
must be low so that the output voltage will remain sufficiently
constant as the current drive changes. In some applications, this
may require that the output of the voltage reference be buffered
by an amplifier with low impedance at relatively high frequen-
cies. In choosing a voltage reference, consideration should be
made for selecting one with low noise. A capacitor connected
between REF IN and AGND will reduce the demands on the
reference by decreasing the magnitude of high frequency com-
ponents required to be sourced by the reference.
Figures 6 and 7 represent typical design approaches.
Figure 6.
Figure 6 shows a voltage reference circuit featuring the 5 V out-
put AD586. The AD586 is a low cost reference which utilizes a
buried Zener architecture to provide low noise and drift. Over
the 0°C to +70°C range, the AD586L grade exhibits less than
2.25 mV output change from its initial value at +25°C. A noise-
reduction capacitor, C
N
, reduces the broadband noise of the
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD676JDZ

Mfr. #:
Buy AD676JDZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit Parallel 100 kSPS Sampling
Lifecycle:
New from this manufacturer.
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