AD676
REV. A
–8–
FUNCTIONAL DESCRIPTION
The AD676 is a multipurpose 16-bit analog-to-digital converter
and includes circuitry which performs an input sample/hold
function, ground sense, and autocalibration. These functions
are segmented onto two monolithic chips—an analog signal pro-
cessor and a digital controller. Both chips are contained within
the AD676 package.
The AD676 employs a successive-approximation technique to
determine the value of the analog input voltage. However, in-
stead of the traditional laser-trimmed resistor-ladder approach,
this device uses a capacitor-array, charge redistribution tech-
nique. Binary-weighted capacitors subdivide the input sample to
perform the actual analog-to-digital conversion. The capacitor
array eliminates variation in the linearity of the device due to
temperature-induced mismatches of resistor values. Since a ca-
pacitor array is used to perform the data conversions, the
sample/hold function is included without the need for additional
external circuitry.
Initial errors in capacitor matching are eliminated by an auto-
calibration circuit within the AD676. This circuit employs an
on-chip microcontroller and a calibration DAC to measure and
compensate capacitor mismatch errors. As each error is deter-
mined, its value is stored in on-chip memory (RAM). Subse-
quent conversions use these RAM values to improve conversion
accuracy. The autocalibration routine may be invoked at any
time. Autocalibration insures high performance while eliminat-
ing the need for any user adjustments and is described in detail
below.
The microcontroller controls all of the various functions within
the AD676. These include the actual successive approximation
algorithm, the autocalibration routine, the sample/hold opera-
tion, and the internal output data latch.
AUTOCALIBRATION
The AD676 achieves rated performance without the need for
user trims or adjustments. This is accomplished through the use
of on-chip autocalibration.
In the autocalibration sequence, sample/hold offset is nulled by
internally connecting the input circuit to the ground sense cir-
cuit. The resulting offset voltage is measured and stored in
RAM for later use. Next, the capacitor representing the most
significant bit (MSB) is charged to the reference voltage. This
charge is then transferred to a capacitor of equal size (composed
of the sum of the remaining lower weight bits). The difference
in the voltage that results and the reference voltage represents
the amount of capacitor mismatch. A calibration digital-to-ana-
log converter (DAC) adds an appropriate value of error correc-
tion voltage to cancel this mismatch. This correction factor is
also stored in RAM. This process is repeated for each of the
capacitors representing the remaining top eight bits. The accu-
mulated values in RAM are then used during subsequent con-
versions to adjust conversion results accordingly.
As shown in Figure 1, when CAL is taken HIGH the AD676 in-
ternal circuitry is reset, the BUSY pin is driven HIGH, and the
ADC prepares for calibration. This is an asynchronous hard-
ware reset and will interrupt any conversion or calibration cur-
rently in progress. Actual calibration begins when CAL is taken
LOW and completes in 85,530 clock cycles, indicated by BUSY
going LOW. During calibration, it is preferable for SAMPLE to
be held LOW. If SAMPLE is HIGH, diagnostic data will appear
on Pins 5 and 6. This data is of no value to the user.
The AD676 requires one clock cycle after BUSY goes LOW to
complete the calibration cycle. If this clock cycle is not pro-
vided, it will be taken from the first conversion, likely resulting
in first conversion error.
In most applications, it is sufficient to calibrate the AD676 only
upon power-up, in which case care should be taken that the
power supplies and voltage reference have stabilized first. If not
calibrated, the AD676 accuracy may be as low as 10 bits.
CONVERSION CONTROL
The AD676 is controlled by two signals: SAMPLE and CLK, as
shown in Figures 2a and 2b. It is assumed that the part has been
calibrated and the digital I/O pins have the levels shown at the
start of the timing diagram.
A conversion consists of an input acquisition followed by 17
clock pulses which execute the 16-bit internal successive ap-
proximation routine. The analog input is acquired by taking the
SAMPLE line HIGH for a minimum sampling time of t
S
. The
actual sample taken is the voltage present on V
IN
one aperture
delay after the SAMPLE line is brought LOW, assuming the
previous conversion has completed (signified by BUSY going
LOW). Care should he taken to ensure that this negative edge is
well defined and jitter free in ac applications to reduce the un-
certainty (noise) in signal acquisition. With SAMPLE going
LOW, the AD676 commits itself to the conversion—the input at
V
IN
is disconnected from the internal capacitor array, BUSY
goes HIGH, and the SAMPLE input will be ignored until the
conversion is completed (when BUSY goes LOW). SAMPLE
must be held LOW for a minimum period of time t
SL
. A period
of time t
SC
after bringing SAMPLE LOW, the 17 CLK cycles
are applied; CLK pulses that start before this period of time are
ignored. BUSY goes HIGH t
SB
after SAMPLE goes LOW, sig-
nifying that a conversion is in process, and remains HIGH until
the conversion is completed. BUSY goes LOW during the 17th
CLK cycle at the point where the data outputs have changed
and are valid. The AD676 will ignore CLK after BUSY has
gone LOW and the output data will remain constant until a new
conversion is completed. The data can, therefore, be read any
time after BUSY goes LOW and before the 17th CLK of the
next conversion (see Figures 2a and 2b). The section on Micro-
processor Interfacing discusses how the AD676 can be inter-
faced to a 16-bit databus.
Typically BUSY would be used to latch the AD676 output data
into buffers or to interrupt microprocessors or DSPs. It is rec-
ommended that the capacitive load on BUSY be minimized by
driving no more than a single logic input. Higher capacitive
loads such as cables or multiple gates may degrade conversion
quality unless BUSY is buffered.
