OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AQD-D4U16R24-SE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
288 Pin DDR4 1.2V 2400 RegDIMM
16GB Based on 1Gx8
AQD-D4U16R24-SE
Advantech
10
1
Timing Parameters & Specifications
Speed DDR4 2400 Unit
Parameter Symbol Min Max
Average Clock Period
tCK 0.833 <0.938 ns
CK high-level width
tCH 0.48 0.52 tCK
CK low-level width tCL 0.48 0.52 tCK
DQS, /DQS to DQ skew, per group, per
access
tDQSQ - 0.16
tCK(avg)
/2
DQ output hold time from DQS, /DQS
tQH 0.76 -
tCK(avg)
/2
DQS_t and DQS_c low-impedance time
(Referenced from RL-1)
tLZ(DQS) -300 150
ps
DQS_t and DQS_c high-impedance time
(Referenced from RL+BL/2)
tHZ(DQS) - 150
ps
DQS_t, DQS_c falling edge setup time to
CK_t, CK_c rising edge
tDSS 0.18 - tCK
DQS_t, DQS_c falling edge hold time
from CK_t, CK_c rising edge
tDSH 0.18
tCK
DQS, /DQS Read preamble
tRPRE
0.9 - tCK
1.8 tCK
DQS, /DQS differential Read postamble
tRPST 0.33 - tCK
DQS, /DQS Write preamble
tWPRE
0.9 - tCK
1.8 NA tCK
DQS, /DQS Write postamble
tWPST 0.33 - tCK
DQS, /DQS differential input low pulse
width
tDQSL 0.46 0.54 tCK
DQS, /DQS differential input high pulse
width
tDQSH 0.46 0.54 tCK
DQS, /DQS rising edge to CK, /CK rising
edge
tDQSS -0.27 +0.27 tCK
DQS, /DQS falling edge setup time to
CK, /CK rising edge
tDSS
0.18 -
tCK
DQS, /DQS falling edge hold time to CK,
/CK rising edge
tDSH 0.18 - tCK
Delay from start of internal write
transaction to internal read com-mand for
different bank group
tWTR_S
max (2nCK, 2.5ns) -
Delay from start of internal write
transaction to internal read com-mand for
same bank group
tWTR_L
max (4nCK,7.5ns)
Write recovery time tWR
15 -
ns
Mode register set command cycle time
tMRD 8 - nCK
CAS_n to CAS_n command delay for
same bank group
tCCD_L
max(5 nCK, 5 ns)
- nCK
288 Pin DDR4 1.2V 2400 RegDIMM
16GB Based on 1Gx8
AQD-D4U16R24-SE
Advantech
11
1
CAS_n to CAS_n command delay for
different bank group
tCCD_S
4 nCK
Auto precharge write recovery +
precharge time
tDAL(min)
Programmed WR + roundup ( tRP / tCK(avg)) nCK
ACTIVATE to ACTIVATE Command
delay to different bank group for 2KB
page size
tRRD_S(2K) Max(4nCK,5 .3ns)
- nCK
Parameter Symbol Min Max Unit
ACTIVATE to ACTIVATE Command
delay to different bank group for 1KB
page size
RRD_S(1K) Max(4nCK,3 .3ns)
- nCK
ACTIVATE to ACTIVATE Command
delay to different bank group for 1/ 2KB
page size
tRRD_S(1/
2K)
Max(4nCK,3 .3ns)
nCK
ACTIVATE to ACTIVATE Command
delay to same bank group for 2KB page
size
tRRD_L(2K) Max(4nCK,6 .4ns)
nCK
ACTIVATE to ACTIVATE Command
delay to same bank group for 1KB page
size
tRRD_L(1K) Max(4nCK,4 .9ns)
nCK
ACTIVATE to ACTIVATE Command
delay to same bank group for 1/2KB
page size
tRRD_L(1/
2K)
Max(4nCK,4 .9ns)
nCK
Four activate window for 2KB page size
tFAW_2K Max(28nCK, 30ns) - ns
Four activate window for 1KB page size
tFAW_1K Max(20nCK, 21ns) ns
Four activate window for 1/2KB page
size
tFAW_1/2K Max(16nCK, 13ns) - ns
Power-up and RESET calibration time
tZQinitl
1024 - nCK
Normal operation Full calibration time tZQoper
512 -
nCK
Normal operation short calibration time tZQcs 128
- nCK
Exit self refresh to commands not
requiring a locked DLL
tXS tRFC(min)+ 10ns
-
Exit self refresh to commands requiring a
locked DLL
tXSDLL tDLLK(min)
-
Internal read to precharge command
delay
tRTP max (4nCK,7.5ns )
-
Minimum CKE low width for Self refresh
entry to exit timing
tCKESR tCKE(min)+ 1nCK
-
Exit power down with DLL to any valid
command: Exit Precharge Power Down
with DLL
tXP max (4nCK,6ns)
-
CKE minimum pulse width (high and low
pulse width)
tCKE max (3nCK, 5ns)
Asynchronous RTT turn-on delay
(Power-Down with DLL frozen)
tAONAS 1.0 9.0
ns
Asynchronous RTT turn-off delay
(Power-Down with DLL frozen)
tAOFAS
1.0 9.0 ns
RTT dynamic change skew tADC
0.3 0.7 ns
288 Pin DDR4 1.2V 2400 RegDIMM
16GB Based on 1Gx8
AQD-D4U16R24-SE
Advantech
12
1
SERIAL PRESENCE DETECT SPECIFICATION
16384MB(2048Mx72Bit ) Serial Presence Detect for DDR4 REG DIMM (PC-19200) 2400 CL=17
BYTE FUNCTION DESCRIDED FUNCTION SUPPORTED HEX VALUE
0 Number of serial PD bytes written/SPD device size/CRC coverage 512B Total, 384B Used 23
1 SPD revision Revision 1.0 10
2 Key byte/DRAM device type DDR4 SDRAM 0C
3 Key byte/module type RegDIMM 01
4 SDRAM density and banks 8Gb, 4BG, 4Banks 85
5 SDRAM addressing 16 rows, 10 columns 21
6 SDRAM package type Monolithic DRAM Device 00
7 SDRAM optional features Unlimited MAC 08
8 SDRAM thermal and refresh options — 00
9 Other SDRAM optional feature sPPR supported 60
10 Reserved — 00
11 Module Nominal Voltage,VDD 1.2V 03
12 Module organization 2Ranks / x8 bits 09
13 Module memory bus width 72 bits / with ECC 0B
14 Module thermal sensor Incorporated 80
15 Reserved — 00
16 Reserved — 00
17 Timebases MTB 125ps, FTB 1ps 00
18 SDRAM minimum cycle time(tCKAVG min) 0.833ns 07
19 SDRAM maximum cycle time(tCKAVG max) 1.5ns 0C
20 CAS latencies supported, first byte CL=10,11,12,13,14,15,16,17,18 F8
21 CAS latencies supported, second byte CL=10,11,12,13,14,15,16,17,18 0F
22 CAS latencies supported, third byte CL=10,11,12,13,14,15,16,17,18 00
23 CAS latencies supported, fourth byte CL=10,11,12,13,14,15,16,17,18 00
24 Minimum CAS latency time(tAA min) 13.75ns 6E
25 Minimum RAS to CAS delay time(tRCD min) 13.75ns 6E
26 Minimum Row precharge delay time(tRP min) 13.75ns 6E
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

AQD-D4U16R24-SE

Mfr. #:
Buy AQD-D4U16R24-SE
Manufacturer:
Advantech
Description:
Memory Modules 16G R-DDR4-2400 1.2V 1GX8 SAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet