288 Pin DDR4 1.2V 2400 RegDIMM
16GB Based on 1Gx8
AQD-D4U16R24-SE
Advantech
13
1
27 Upper nibbles for tRAS min and tRC min tRAS = 32ns, tRC = 45.75ns 11
28 Minimum active to precharge delay time(tRAS min), least significant byte 32ns 00
29 Minimum active to active/refresh delay time(tRC min), least significant byte 45.75ns 6E
30 Minimum refresh recovery delay time(tRFC1 min), LSB 350ns F0
31 Minimum refresh recovery delay time(tRFC1 min), MSB 350ns 0A
32 Minimum refresh recovery delay time(tRFC2 min), LSB 260ns 20
33 Minimum refresh recovery delay time(tRFC2 min), MSB 260ns 08
34 Minimum refresh recovery delay time(tRFC4 min), LSB 160ns 00
35 Minimum refresh recovery delay time(tRFC4 min), MSB 160ns 05
36 Minimum four activate window time(tFAW min), most significant nibble 21ns 00
37 Minimum four activate window time(tFAW min), least significant byte 21ns A8
38 Minimum activate to activate delay time(tRRD_S min), different bank group 3.3ns 1B
39 Minimum activate to activate delay time(tRRD_L min), same bank group 4.9ns 28
40 Minimum CAS to CAS delay time(tCCD_L min), same bank group 5ns 28
41 Upper Nibble for tWR min 15ns 00
42 Minimum Write Recovery Time (tWR min) 15ns 78
43 Upper Nibbles for tWTR min 2.5ns 00
44 Minimum Write to Read Time (tWTR_S min), different bank group 2.5ns 14
45 Minimum Write to Read Time (tWTR_L min), same bank group 7.5ns 3C
46-59 Reserved — 00
60 Connector to SRAM bit mapping DQ0 - 3 0C
61 Connector to SRAM bit mapping DQ4 - 7 2C
62 Connector to SRAM bit mapping DQ8 - 11 0C
63 Connector to SRAM bit mapping DQ12 - 15 2C
64 Connector to SRAM bit mapping DQ16 - 19 0C
65 Connector to SRAM bit mapping DQ20 - 23 2C
66 Connector to SRAM bit mapping DQ24 - 27 0C
67 Connector to SRAM bit mapping DQ28 - 31 2C
68 Connector to SRAM bit mapping CB0 - 3 0C
