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MAX4550CAI+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
MAX4550/MAX4570
Serially Controlled, Dual 4x2, Clickless
Audio/Video Analog Crosspoint Switches
10 ______________________________________________________________________________________
Detailed Description
The MAX4550/MAX4570 are serial-interface, program-
mable, dual 4x2 audio/video crosspoint switches. Each
device contains two independent 4x2 crosspoint
switches, controlled through the on-chip serial inter-
face. The MAX4550 uses a 2-wire I
2
C-compatible serial
communications protocol, while the MAX4570 uses a
3-wire SPI/QSPI/MICROWIRE-compatible serial com-
munications protocol.
These ICs include four controllable auxiliary outputs,
each capable of sourcing 1mA or sinking 12mA. Also
included are four selectable bias-resistor networks (one
for each output) for use with AC-coupled input signals.
Both devices operate with either ±5V dual supplies or a
single +5V supply, and are optimized for use in the
audio frequency range to 20kHz and at video frequen-
cies up to 4MHz. They feature 80Ω on-resistance, 10Ω
on-resistance matching between channels, 5Ω on-
resistance flatness, and as low as 0.004% total harmon-
ic distortion.
The MAX4550/MAX4570 offer better than -110dB of
audio off-isolation, -95dB of audio crosstalk, -78dB of
video off-isolation, and -54dB of video crosstalk
(4MHz). The SA and SB (shunt) inputs further improve
off-isolation, allowing for the addition of external shunt
capacitors or the connection of outputs to AC grounds.
These devices feature a clickless operation mode for
noiseless audio switching. Clickless or standard switch-
ing mode is selectable for each individual output using
the serial interface.
__________
Applications Information
The MAX4550/MAX4570 are divided into five functional
blocks: the control-logic block, two switch-matrix
blocks, the bias-resistor block, and the auxiliary-output
block (see
Functional Diagram
). The control-logic block
accepts commands via the serial interface and uses
those commands to control the four remaining blocks.
Command-Byte and Data-Byte
Programming
The devices are programmed through their serial inter-
face with a command byte followed by a data byte.
Each bit of the command byte selects one of the func-
tional blocks to be controlled by the subsequent data
byte. The data byte sets the state of the selected
block(s). For the two switch-matrix blocks, the data
byte sets the switch state. For the bias-resistor block,
the data byte controls which bias network is active. For
the auxiliary-output block, the data byte programs the
state of the four auxiliary outputs (see
Functional
Diagram
).
A logic “1” in any bit position of the data byte makes
that function active, while a logic “0” makes it inactive.
Tables 1–4 describe the command byte and the corre-
sponding data byte. For example, if bit C4 of the com-
mand byte is set, the subsequent data byte programs
the state of the auxiliary outputs. If bits D0 and D2 of
the subsequent data byte are set, Q0 and Q2 outputs
are set high. If more than one bit of the command byte
is set, the data byte programs all of the corresponding
blocks. This operation is useful, for instance, to simulta-
neously set both switch matrices to the same configura-
tion. Any block that is not selected in the command
byte remains unchanged.
Don’t careC7
Don’t careC6
BIT REGISTER
BIAS/MODEC5
AUXC4
COM2A
COM2BC3
C1
COM1AC0
COM1BC2
Don’t care
Don’t careD7
D5
Controls the switch connected to S_ ;
1 = close switch, 0 = open switch.
D4
Controls the switch connected to NO2_ ;
1 = close switch, 0 = open switch.
Don’t careD6
Controls the switch connected to NO4_ ;
1 = close switch, 0 = open switch.
D3
D1
Controls the switch connected to NO1_ ;
1 = close switch, 0 = open switch.
DESCRIPTION
D0
Controls the switch connected to NO3_ ;
1 = close switch, 0 = open switch.
D2
BIT
Table 2. COM Data-Byte Format
(C0, C1, C2, C3 = “1”)
Table 1. Command-Byte Format
Table 3. AUX_ Data-Byte Format (C4 = “1”)
Table 4. Clickless Mode/BIAS_ Data-Byte
Format (C5 = “1”)
2-Wire Serial Interface
The MAX4550 uses a 2-wire, fast-mode, I
2
C-compatible
serial interface. This protocol consists of an address
byte followed by the command and data bytes. To
address a given chip, the A0 and A1 bits in the
address byte must duplicate the values present at the
A0 and A1 pins of that chip. The rest of the address
bits control MAX4550 operation. The command and
data-byte details are described in the
Command-Byte
and Data-Byte Programming
section.
The 2-wire serial interface requires only two I/O lines of
a standard microprocessor port. Figures 1 and 2 detail
the timing diagram for signals on the 2-wire bus, and
Table 5 details the format of the signals. The MAX4550
is a receive-only device and must be controlled by a
bus master device. A bus master device communicates
by transmitting the address byte of the slave device
over the bus and then transmitting the desired informa-
tion. Each transmission consists of a start condition, the
MAX4550’s programmable slave-address byte, a com-
mand-byte, a data-byte, and finally a stop condition.
The slave device acknowledges the recognition of its
address by pulling the SDA line low for one clock peri-
od after the address byte is transmitted. The slave
device also issues a similar acknowledgment after the
command byte and again after the data byte.
Start and Stop Conditions
The bus-master signals the beginning of a transmission
with a start condition by transitioning SDA from high to
low while SCL is high. When the master has finished
communicating with the slave, it issues a stop condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
Slave Address (Address Byte)
The MAX4550 uses an 8-bit-long slave address. To
select a slave address, connect A0 and A1 to V+ or
GND. The MAX4550 has four possible slave addresses,
thus a maximum of four of these devices may share the
same 2-bit address bus. The slave device (MAX4550)
monitors the serial bus continuously, waiting for a start
condition followed by an address byte. When a slave
device recognizes its address (10011A
1
A
0
0), it
acknowledges that it is ready for further communication
by pulling the SDA line low while SCL is high.
3-Wire Serial Interface
The MAX4570 3-wire serial interface is SPI/
QSPI/MICROWIRE-compatible. An active-low chip-
select (CS) input enables the device to receive data
from the serial input (DIN). Data is clocked in on the ris-
ing edge of the serial-clock (SCLK) signal. A total of 16
bits are needed in each write cycle. Segmented write
cycles are allowed (two 8-bit-wide transfers) if CS
remains low. The first bit clocked into the MAX4550 is
the command byte’s MSB, and the last bit clocked in is
the data byte’s LSB. While shifting data, the device
remains in its original configuration. After all 16 bits are
clocked into the input shift register, a rising edge on CS
latches the data into the MAX4570 internal registers,
initiating the device’s change of state.
MAX4550/MAX4570
Serially Controlled, Dual 4x2, Clickless
Audio/Video Analog Crosspoint Switches
______________________________________________________________________________________ 11
Don’t care
Don’t careD7
D5
Don’t careD4
Controls output Q1; 1 = set output high,
0 = set output low.
Don’t careD6
Controls output Q3; 1 = set output high,
0 = set output low.
D3
D1
Controls output Q0; 1 = set output high,
0 = set output low.
DESCRIPTION
D0
Controls output Q2; 1 = set output high,
0 = set output low.
D2
BIT
Controls COM2A clickless mode; 1 = enables
clickless mode, 0 = disables clickless mode.
Controls COM2B clickless mode; 1 = enables
clickless mode, 0 = disables clickless mode.
D7
D5
Controls COM1A clickless mode; 1 = enables
clickless mode, 0 = disables clickless mode.
D4
Controls COM2A bias resistors; 1 = connect bias
resistors, 0 = disconnect bias resistors.
Controls COM1B clickless mode; 1 = enables
clickless mode, 0 = disables clickless mode.
D6
Controls COM2B bias resistors; 1 = connect bias
resistors, 0 = disconnect bias resistors.
D3
D1
Controls COM1A bias resistors; 1 = connect bias
resistors, 0 = disconnect bias resistors.
DESCRIPTION
D0
Controls COM1B bias resistors; 1 = connect bias
resistors, 0 = disconnect bias resistors.
D2
BIT
MAX4550/MAX4570
Serially Controlled, Dual 4x2, Clickless
Audio/Video Analog Crosspoint Switches
12 ______________________________________________________________________________________
SCL
SDA
ACKACK
SRT
ACK
A7 D0D0
A0 D7 D7
STOP
Figure 1. 2-Wire Serial-Interface Timing Diagram
SCL
A B C D
E
F G
H
I
J
SDA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
A = START CONDITION
B = MSB OF ADDRESS BYTE
C = LSB OF ADDRESS BYTE
D = ACKNOWLEDGE CLOCKED INTO MASTER
E = MSB OF COMMAND BYTE
F = LSB OF COMMAND BYTE
G = ACKNOWLEDGE CLOCKED INTO MASTER
H = MSB OF DATA BYTE
I = LSB OF DATA BYTE
J = ACKNOWLEDGE CLOCKED INTO MASTER
Figure 2. 2-Wire Serial-Interface Timing Details
Table 5. 2-Wire Serial-Interface Data Format
0 1
A
5
A
4
ADDRESS BYTE
A
0
0 B
I
A
S
A
U
X
1S
R
T
A
1
A
0
1 A
1
0
C
5
C
4
COMMAND BYTE
C
O
M
2
A
C
O
M
1
A
XA
C
K
C
1
C
0
C
O
M
2
B
C
O
M
1
B
A
3
A
2
X
C
3
C
2
C
7
C
6
D
5
D
4
D
5
D
4
DATA BYTE
D
1
D
0
D
7
A
C
K
D
1
D
0
D
3
D
2
D
6
D
3
D
2
D
7
D
6
A
C
K
A
7
A
6
X = Don’t care
SRT = Start condition
ACK = Acknowledge condition
STOP = Stop condition
S
T
O
P
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MAX4550CAI+

Mfr. #:
Buy MAX4550CAI+
Manufacturer:
Maxim Integrated
Description:
Analog & Digital Crosspoint ICs Dual 4x2 A/V Crosspoint Switch
Lifecycle:
New from this manufacturer.
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