17
LTC1409
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Figure 13d. Suggested Evaluation Circuit Board Solder Side Layout
Digital Interface
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 0.9µs, and a maximum conversion time over the
full operating temperature range of 1.15µs. No external
adjustments are required. The guaranteed maximum ac-
quisition time is 150ns. In addition, a throughput time of
1250ns and a minimum sample rate of 800ksps is guaran-
teed.
Power Shutdown
The LTC1409 provides two power Shutdown modes, Nap
and Sleep, to save power during inactive periods. The
Nap mode reduces the power by 95% and leaves only the
digital logic and reference powered up. The wake-up time
from Nap to active is 200ns. In Sleep mode all bias
currents are shut down and only leakage current re-
mains, about 1µA. Wake-up time from Sleep mode is
much slower since the reference circuit must power up
and settle to 0.01% for full 12-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
10ms with the recommended 10µF capacitor.
Shutdown is controlled by Pin 21 (SHDN). The ADC is in
shutdown when it is low. The Shutdown mode is selected
with Pin 20 (NAP/SLP); high selects Nap.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY
is low during a conversion.
Figures 16 through 20 show several different modes of
operation. In modes 1a and 1b (Figures 16 and 17) CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
