7
LTC1409
PI FU CTIO S
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CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. The input must be low for the
ADC to recognize CONVST and RD inputs.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
V
SS
(Pin 26):5V Negative Supply. Bypass to AGND
using 10µF tantalum in parallel 0.1µF or 10µF ceramic.
OV
DD
(Pin 27): Positive Supply for Output Drivers. For
5V logic, short to Pin 28. For 3V logic, short to supply
of the logic being driven.
AV
DD
(Pin 28): 5V Positive Supply. Bypass to AGND
10µF tantalum in parallel with 0.1µF or 10µF ceramic.
Load Circuits for Bus Relinquish Time
Load Circuits for Access Timing
1k 100pF 100pF
DBN
DBN
1k
5V
LTC1409 • TC02
1k C
L
C
L
DBN DBN
1k
5V
LTC1409 • TC01
(a) Hi-Z to V
OH
and V
OL
to V
OH
(b) Hi-Z to V
OL
and V
OH
to V
OL
(a) V
OH
to Hi-Z (b) V
OL
to Hi-Z
FU CTIO AL BLOCK DIAGRA
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12-BIT CAPACITIVE DAC
COMPREF AMP
2.5V REF
4k
REFCOMP
(4.06V)
C
SAMPLE
C
SAMPLE
•
•
D11
D0
BUSY
CONTROL LOGIC
CSCONVSTRDSHDN
INTERNAL
CLOCK
NAP/SLP
ZEROING SWITCHES
OV
DD
OGND
AV
DD
+A
IN
–A
IN
V
REF
AGND
DGND
12
LTC1409 • BD
+
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
TEST CIRCUITS
8
LTC1409
APPLICATIONS INFORMATION
WUU
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CONVERSION DETAILS
The LTC1409 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the +A
IN
and –A
IN
inputs are
connected to the sample-and-hold capacitors (C
SAMPLE
)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 150ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the C
SAMPLE
capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DACs output balances the +A
IN
and –A
IN
input
charges. The SAR contents (a 12-bit data word) which
represents the difference of +A
IN
and –A
IN
are loaded into
the 12-bit output latches.
DYNAMIC PERFORMANCE
The LTC1409 has excellent high speed sampling capabil-
ity. FFT (Fast Four Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. Figure 2 shows typical
LTC1409 plots.
Figure 1. Simplified Block Diagram
COMP
+C
SAMPLE
–C
DAC
•
•
D11
D0
ZEROING SWITCHES
HOLD
HOLD
+A
IN
–A
IN
+C
DAC
–C
SAMPLE
12
LTC1409 • F01
+
SAR
OUTPUT
LATCHES
+V
DAC
–V
DAC
HOLD
HOLD
Figure 2b. LTC1409 Nonaveraged, 4096 Point FFT,
Input Frequency = 375kHz
FREQUENCY (kHz)
0
AMPLITUDE (dB)
100 200
300
400
LT1409 • F02b
0
20
40
60
80
100
120
50 150
250
350
f
SAMPLE
= 800kHz
f
IN
= 375kHz
SFDR = 89dB
SINAD = 72.5dB
Figure 2a. LTC1409 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
FREQUENCY (kHz)
0
AMPLITUDE (dB)
100 200
300
400
LT1409 • F02a
0
20
40
60
80
100
120
50 150
250
350
f
SAMPLE
= 800kHz
f
IN
= 97.45kHz
SFDR = 89.1dB
SINAD = 73.1dB
9
LTC1409
APPLICATIONS INFORMATION
WUU
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Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
an 800kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 400kHz.
Effective Number of Bits
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) – 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 800kHz the LTC1409 maintains near ideal ENOBs
up to the Nyquist input frequency of 400kHz. Refer to
Figure 3.
THD
VVV Vn
V
=
+++
20 Log
234
1
222 2
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through Nth harmonics. THD vs input frequency is
shown in Figure 4. The LTC1409 has good distortion
performance up to the Nyquist frequency and beyond.
INPUT FREQUENCY (Hz)
EFFECTIVE BITS
12
11
10
9
8
7
6
5
4
3
2
1
0
1k 100k 1M 10M
LTC1409 • F03
10k
f
SAMPLE
= 800kHz
Figure 3. Effective Bits and Signal/(Noise +
Distortion) vs Input Frequency
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the DC transfer function
can create distortion products at the sum and difference
frequencies of mfa + –nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb). If
the two input sine waves are equal in magnitude, the value
(in decibels) of the 2nd order IMD products can be
expressed by the following formula:
IMD fa fb+
()
=20 Log
Amplitude at (fa + fb)
Amplitude at fa
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This

LTC1409CSW#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-bit, 800ksps SAR ADC with +/-2.5V Input
Lifecycle:
New from this manufacturer.
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