ISL29035
10
FN8371.3
December 12, 2016
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Register Description
Following are detailed descriptions of the control registers
related to the operation of the ISL29035 ambient light sensor
device. These registers are accessed by the I
2
C serial interface.
For details on the I
2
C interface, refer to “Serial Interface” on
page 7.
All the features of the device are controlled by the registers. The
ADC data can also be read. The following sections explain the
details of each register bit. All RESERVED bits are Intersil used
bits ONLY. The value of the reserved bit can change without
notice.
Decimal to Hexadecimal Conversion
To convert decimal value to hexadecimal value, divide the
decimal number by 16 and write the remainder on the side as
the least significant digit. This process is continued by dividing
the quotient by 16 and writing the remainder until the quotient
is 0. When performing the division, the remainders, which will
represent the hexadecimal equivalent of the decimal number,
are written beginning with the least significant digit (right) and
each new digit is written to the next most significant digit (the
left) of the previous digit. Consider the number 175 decimal.
Command-I Register (Address: 0x00)
The Command-I register consists of control and status bits. In
this register, there are two interrupt persist bits, one interrupt
status bit and three operation mode bits. The operation mode
bits and the interrupt persist bits are independent of each other.
The default register value is 0x00 at power-on.
INTERRUPT PERSIST BITS (B0-B1)
The interrupt persist bits provide control over when interrupts
occur. There are four different selections for this feature. A value
of n (where n is 1, 4, 8, and 16) results in an interrupt only if the
value remains outside the threshold window for n consecutive
integration cycles. For example, if n is equal to 16 and the ADC
resolution is set to 16-bits, then the integration time is 105ms.
An interrupt is generated whenever the last conversion results in
a value outside of the programmed threshold window. The
interrupt is active-low and remains asserted until cleared by
writing the COMMAND register with the CLEAR bit set. Table 5
lists the possible interrupt persist bits.
INTERRUPT STATUS BIT (B2)
The interrupt status bit (INT) is a status bit for light intensity
detection. The bit is set to logic HIGH when the light intensity
crosses the interrupt thresholds window (register address
0x04 - 0x07), and set to logic LOW when it is within the interrupt
thresholds window. Once the interrupt is triggered, the INT
pin
goes low and the interrupt status bit goes HIGH until the status
bit is polled through the I
2
C read command. Both the INT pin and
the interrupt status bit are automatically cleared at the end of
the 8-bit Device Register byte (0x00) transfer. Table 6
shows the
interrupt status states.
TABLE 2. REGISTER MAP
NAME
REGISTER
ADDRESS REGISTER BITS
DEFAULT ACCESSDEC HEX B7 B6 B5 B4 B3 B2 B1 B0
COMMAND-I 0 0x00 OP2 OP1 OP0 RESERVED INT
PRST1 PRST0 0x00 RW
COMMAND-II 1 0x01 RESERVED RES1 RES0 RANGE1 RANGE0 0x00 RW
DATA
LSB
20x02D7D6D5D4D3D2D1D00x00RO
DATA
MSB
3 0x03 D15 D14 D13 D12 D11 D10 D9 D8 0x00 RO
INT_LT_LSB 4 0x04 TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0 0x00 RW
INT_LT_MSB 5 0x05 TL15 TL14 TL13 TL12 TL11 TL10 TL9 TL8 0x00 RW
INT_HT_LSB 6 0x06 TH7 TH6 TH5 TH4 TH3 TH2 TH1 TH0 0xFF RW
INT_HT_MSB 7 0x07 TH15 TH14 TH13 TH12 TH11 TH10 TH9 TH8 0xFF RW
ID 15 0x0F BOUT RESERVED 1 0 1 RESERVED 1x101xxx RW
TABLE 3. DECIMAL TO HEXADECIMAL
DIVISION QUOTIENT REMAINDER HEX NUMBER
175/16 10 = A 15 = F 0xAF
TABLE 4. COMMAND-I REGISTER ADDRESS
NAME
ADDR
(HEX)
REGISTER BITS
DFLT
(HEX)B7 B6 B5 B4 B3 B2 B1 B0
COMMAND-I 0x00 OP
2
OP
1
OP
0
RESERVED INT
PRST
1
PRST
0
0x00
TABLE 5. INTERRUPT PERSIST BITS
B1 B0
NUMBER OF INTEGRATION
CYCLES (n)
00 1
01 4
10 8
11 16
TABLE 6. INTERRUPT STATUS BIT (INT
)
BIT 2 OPERATION
0 Interrupt is cleared or not triggered yet
1 Interrupt is triggered
