ISL29035
4
FN8371.3
December 12, 2016
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I
2
C Interface Specifications V
DD
= 3.0V, T
A
= +25°C, 16-bit ADC operation, unless otherwise specified.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7
)TYP
MAX
(Note 7)UNIT
SDA and SCL Input Buffer LOW Voltage V
IL
0.55 V
SDA and SCL Input Buffer HIGH Voltage V
IH
1.25 V
SDA and SCL Input Buffer Hysteresis V
Hys
(Note 8)
0.05 x
V
DD
V
SDA Output Buffer LOW Voltage
(Open-Drain), Sinking 4mA
V
OL
(Note 8)
0 0.06 0.4 V
SDA and SCL Pin Capacitance C
PIN
(Note 8)
T
A
= +25°C, f = 1MHz, V
DD
= 5V, V
IN
=0V,
V
OUT
= 0V
10 pF
SCL Frequency f
SCL
400 kHz
Pulse Width Suppression Time at SDA
and SCL Inputs
t
IN
Any pulse narrower than the maximum
specification is suppressed
50 ns
SCL Falling Edge to SDA Output Data Valid t
AA
900 ns
Time the Bus Must be Free before the
Start of a New Transmission
t
BUF
1300 ns
Clock LOW Time t
LOW
1300 ns
Clock HIGH Time t
HIGH
600 ns
START Condition Set-Up Time t
SU:STA
600 ns
START Condition Hold Time t
HD:STA
600 ns
Input Data Set-Up Time t
SU:DAT
100 ns
Input Data Hold Time t
HD:DAT
30 ns
STOP Condition Set-Up Time t
SU:STO
600 ns
STOP Condition Hold Time t
HD:STO
600 ns
Output Data Hold Time t
DH
0ns
SDA and SCL Rise Time t
R
(Note 8)
20 + 0.1 x
Cb
ns
SDA and SCL Fall Time t
F
(Note 8)
20 + 0.1 x
Cb
ns
Capacitive Loading of SDA or SCL C
b
(Note 10)
Total on-chip and off-chip 400 pF
SDA and SCL Bus Pull-Up Resistor
Off-Chip
R
PU
(Note 8)
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2kΩ ~ 2.5kΩ
For Cb = 40pF, max is about 15kΩ ~ 20kΩ
1k
NOTES:
8. Limits should be considered typical and are not production tested.
9. These are I
2
C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
10. C
b
is the capacitance of the bus in pF.
