Data Sheet AD9665
Rev. F | Page 13 of 16
OPERATION
PIN DESCRIPTIONS
Table 5.
Pin No. Mnemonic Description
1
W3DISN
Negative Enable for Write Channel 3
(LVDS Mode Only).
2 W3DIS Positive Enable for Write Channel 3
(LVDS Mode), Enable (TTL Mode).
3, 4 GND Ground.
5
W2DISN
Negative Enable for Write Channel 2
(LVDS Mode Only).
6 W2DIS Positive Enable for Write Channel 2
(LVDS Mode), Enable (TTL Mode).
7
W1DISN
Negative Enable for Write Channel 1
(LVDS Mode Only).
8 W1DIS Positive Enable for Write Channel 1
(LVDS Mode), Enable (TTL Mode).
9
RDIS
Enable for R Channel (TTL Only).
10 V
DD
5 V Supply and DC Logic Level
for
RDIS
and ENABLE.
11 V
DD
5 V Supply and DC Logic Level
for
RDIS
and ENABLE.
12 W3SET Input for Write Channel 3 (R
IN
= 200 Ω).
13 W2SET Input for Write Channel 2 (R
IN
= 200 Ω).
14 W1SET Input for Write Channel 1 (R
IN
= 200 Ω).
15 RSET Input for Read Channel (R
IN
= 200 Ω).
16 ENABLE Chip Enable—Active High.
17 V
DD
Output Stage Supply, 5 V.
18, 19 LD2 Output 2.
20 GND Ground.
21, 22 LD1 Output 1.
23 V
DD
Output Stage Supply, 5 V.
24 INS Logic mode select (0 = TTL, 1 = LVDS).
25 A
ADJ2
Amplitude Resistor Set for Oscillator 2.
ADJ1
Amplitude Resistor Set for Oscillator 1.
ADJ2
Frequency Resistor Set for Oscillator 2.
28 F
ADJ1
Frequency Resistor Set for Oscillator 1.
29 OUTSEL Output Select (0 = LD2, 1 = LD1).
30 OSCEN Oscillator Enable—Active High.
31 DNC Do not connect. Leave this pin floating
with no external connection.
32 V
DD
5 V Supply and DC Logic Level for OSCEN.
N/A EPAD Exposed Pad. When pulling a high current,
attach heat sink on the exposed pad.
The logic signals, WxDIS,
WxDISN
,
RDIS
, ENABLE, INS,
OUTSEL, and OSCEN, can be driven with pulsed sources or
can be set to a steady state level with jumpers. For steady state
operation, the logic levels for the WxDIS and
WxDISN
pins are
set with voltages applied to the VDPOS and VDNEG pins on
the evaluation board. For LVDS mode (INS = 1), VDPOS and
VDNEG should be at a level greater than 50 mV and less than
2.45 V (0.050 V < VDPOS < 2.45 V and 0.05 V < VDNEG < 2.45 V),
with the differential voltage greater than 100 mV and less than
600 mV. For TTL operation (INS = 0), VDPOS should be
greater than 2.5 V and VDNEG should be less than 0.8 V. Under
TTL operation, it may be convenient to put VDPOS at 5 V and
VDNEG at 0 V. The pin labeled 5 V is the logic level for INS
and OUTSEL.
The V
DD
pins are connected together in the IC and can be
connected to the same external supply. Although they are all
connected internally, there must be a direct connection to each
of these pins through their vector pins externally, which are also
labeled V
DD
.
A jumper set to the right side of a 3-lead connection applies the
VDPOS voltage to the applicable pin on the IC. A jumper set to
the left side of a 3-lead connection applies the VDNEG voltage.
Evaluation boards are shipped with 100 Ω termination resistors
across the LVDS inputs and without 50 Ω resistors on the other
logic traces. Resistors R5 and R8 can be connected between ground
and the cathodes of Diode 1 and Diode 2, respectively. To monitor
diode current with an oscilloscope, a 3.1 Ω resistor can be placed in
each of these positions. The series 46.4 Ω resistors at R4 and R9
present a 50 Ω impedance to measurement equipment. This results
in the oscilloscope displaying the diode current with a conversion
factor of 1.558 mV/mA. If this capability is not desired, 0 Ω
resistors can be installed in the R5 and R8 positions.
