NTB5404N, NTP5404N, NVB5404N
www.onsemi.com
4
TYPICAL PERFORMANCE CURVES
Figure 7. Capacitance Variation
Figure 8. Gate−To−Source and
Drain−To−Source Voltage vs. Total Charge
5
0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
I
S
, SOURCE CURRENT (AMPS)
V
GS
= 0 V
T
J
= 25°C
25
Figure 10. Diode Forward Voltage vs. Current
0.80.6
20
15
R
G
, GATE RESISTANCE (OHMS)
1 10 100
10
1
t, TIME (ns)
V
DS
= 32 V
I
D
= 40 A
V
GS
= 10 V
t
r
t
d(on)
1000
t
f
t
d(off)
10
30
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
0
6
0
Q
G
, TOTAL GATE CHARGE (nC)
10
20 40 60
I
D
= 40 A
T
J
= 25°C
V
GS
Q
GS
140
Q
GD
QT
4
2
10080
0.4 0.70.5
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
18
0
24
12
6
V
DS
V
DS
= 0 V V
GS
= 0 V
15 201010 35
4000
2000
0
40
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
T
J
= 25°C
C
oss
C
iss
C
rss
8000
550
6000
V
GS
V
DS
3025
10000
C
rss
C
iss
120
100
0.9 1 1.1
8
30
35
40
I
D
, DRAIN CURRENT (AMPS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0.1 1
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
10 100
100
V
GS
= 10 V
SINGLE PULSE
T
C
= 25°C
1 mS
100 S
10 mS
dc
10 S
0.001
1
0.1
0.01
