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ICE3PCS01GXUMA1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
CCM-PFC
ICE3PCS01G
Functional Description
Version 3.0 10 03 April 2017
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
output voltage of integrated PI compensator. This block
has been designed to reduce the voltage loop
dependency on the input voltage in order to support the
wide input voltage range (85VAC-265VAC). Figure 7
gives the relative output power transfer curve versus
the digital word from the integrated PI compensator.
The output power at the input voltage of 85VAC and
maximum digital word of 256 from PI compensator is
set as the normative power and the power curves at
different input voltage present the relative power to the
normative one.
Figure 7 Power Transfer Curve
3.6 Average Current Control
The choke current is sensed through the voltage
across the shunt resistor and averaged by the ICOMP
pin capacitor so that the IC can control the choke
current to track the instant variation of the input voltage.
3.6.1 Complete Current Loop
The complete system current loop is shown in Figure 8.
It consists of the current loop block which averages the
voltage at ISENSE pin resulted from the inductor
current flowing across R
shunt
. The averaged waveform
is compared with an internal ramp in the ramp
generator and PWM block. Once the ramp crosses the
average waveform, the comparator C10 turns on the
driver stage through the PWM logic block. The
Nonlinear Gain block defines the amplitude of the
inductor current. The following sections describe the
functionality of each individual blocks.
Figure 8 Complete System Current Loop
3.6.2 Current Loop Compensation
The compensation of the current loop is implemented
at the ICOMP pin. This is OTA6 output and a capacitor
C
ICOMP
has to be installed at this node to ground (see
Figure 8). Under normal mode of the operation, this pin
gives a voltage which is proportional to the averaged
inductor current. This pin is internally shorted to 5V in
the event of standby mode.
3.6.3 Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous mode (CCM) to achieve the power factor
correction. Assuming the loop voltage is working and
output voltage is kept constant, the off duty cycle D
OFF
for a CCM PFC system is given as:
D
OFF
=V
IN
/V
OUT
From the above equation, D
OFF
is proportional to V
IN
.
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle D
OFF
, and thus to the input voltage
V
IN
. Figure 9 shows the scheme to achieve the
objective.
0.00001
0.00010
0.00100
0.01000
0.10000
1.00000
10.00000
0 18 37 55 73 91 110 128 146 165 183 201 219 238 256
PI digital output
relative output power
power at 85V power at 265V
Rectified
Input Voltage
D
B
C
B
L
Boost
Q
B
R
GATE
R
shunt
R
CS
R
S
Gate
Driver
GATE
OTA6
ICOMP
5V
Current Loop
Compensation
Current Loop
Nonlinear
Gain
5.0mS
+/-50uA (linear range)
C
ICOMP
S2
Fault
ISENSE
C10
PWM
Comparator
PWM Logic
Q
Input From
Voltage Loop
volt age
proportional to
averaged
Induc tor current
CCM-PFC
ICE3PCS01G
Functional Description
Version 3.0 11 03 April 2017
Figure 9 Average Current Control in CCM
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 4
(ICOMP). The PWM cycles starts with the Gate turn off
for a duration of T
OFFMIN
(600ns typ.) and the ramp is
kept discharged. The ramp is allowed to rise after the
T
OFFMIN
expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D
OFF
.
Figure 10 shows the timing diagrams of the T
OFFMIN
and
the gate waveforms.
Figure 10 Ramp and PWM waveforms
3.7 PWM Logic
The PWM logic block prioritizes the control input signal
and generates the final logic signal to turn on the driver
stage. The speed of the logic gates in this block,
together with the width of the reset pulse T
OFFMIN
, are
designed to meet a maximum duty cycle D
MAX
of 95%
at the GATE output under 65kHz of operation.
In case of high input currents which results in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal T
OFFMIN
resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 11.
Figure 11 PWM LOGIC
3.8 System Protection
The IC provides numerous protection features in order
to ensure the PFC system in safe operation.
3.8.1 Input Voltage Brownout Protection(BOP)
Brownout occurs when the input voltage V
IN
falls below
the minimum input voltage of the design (i.e. 85V for
universal input voltage range) and the V
CC
has not
entered into the V
CCUVLO
level yet. For a system without
BOP, the boost converter will increasingly draw a
higher current from the mains at a given output power
which may exceed the maximum design values of the
input current.
ICE3PCS01G provides a new BOP feature whereby it
senses directly the input voltage for Input Brown-Out
condition via an external resistor/capacitor/diode
network shown in Figure 12. This network provides a
filtered value of VIN which turns the IC on when the
voltage at pin 9 (BOP) is more than 1.25V. The IC
enters into the fault mode when BOP goes below 1.0V.
The hysteresis prevents the system to oscillate
between normal and fault mode. Note also that the
peak of VIN needs to be at least 20% of the rated V
OUT
in order to overcome OLP and powerup system.
Ramp Profile Ave (I
in
) at ICOMP
Gate
Drive
t
t
PWM Cycle
Ramp
Released
T
off_min
600 ns
Clock
V
C,ref
(1 )
V
ram p
GATE
(1)
V
c,ref
is a function of V
IC OMP
R
S
Q
Q
Curr ent
limit Latch
R
S
Q
Q
PWM on
Latch
High = turn on Gate
T
off_min
600ns
Peak curr ent limit
Current loop
PW M on si gnal
CCM-PFC
ICE3PCS01G
Functional Description
Version 3.0 12 03 April 2017
Figure 12 Input Brownout Protection
3.8.2 Peak Current Limit (PCL)
The IC provides a cycle by cycle peak current limitation
(PCL). It is active when the voltage at pin 2 (ISENSE)
reaches -0.2V. This voltage is amplified by a factor of -
5 and connected to comparator with a reference
voltage of 1.0V as shown in Figure 13. A deglitcher with
200ns after the comparator improves noise immunity to
the activation of this protection.
Figure 13 Peak Current Limit (PCL)
3.8.3 Open Loop Protection (OLP)
Whenever VSENSE voltage falls below 0.5V, or
equivalently V
OUT
falls below 20% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage V
IN
for
normal operation. It is implemented using comparator
C2a with a threshold of 0.5V as shown in the IC block
diagram in Figure 6.
3.8.4 First Over-Voltage Protection (OVP1)
Whenever V
OUT
exceeds the rated value by 8%, the
over-voltage protection OVP1 is active as shown in
Figure 6. This is implemented by sensing the voltage at
VSENSE pin with respect to a reference voltage of
2.7V. A VSENSE voltage higher than 2.7V will
immediately turn off the gate, thereby preventing
damage to bus capacitor. After bulk voltage falls below
the rated value, gate drive resumes switching again.
3.8.5 Second Over Voltage Protection (OVP2)
The second OVP is provided in case that the first one
fails due to the aging or incorrect resistors connected to
the VSENSE pin. This is implemented by sensing the
voltage at pin OVP with respect to a reference voltage
of 2.5V. When voltage at OVP pin is higher than 2.5V,
the IC will immediately turn off the gate, thereby
preventing damage to bus capacitor.
When the bulk voltage drops out of the hysteresis the
IC can be latched further or begin auto soft-start. These
two protection modes are distinguished through
detecting the external equivalent resistance connecting
to VBTHL_EN pin after Vcc is higher than UVLO
threshold as shown in Figure 3. If the equivalent
resistance is higher than 100kΩ the IC selects latch
mode for second OVP, otherwise auto soft-start mode.
In normal operation the trigger level of second OVP
should be designed higher than the first. However in
the condition of mains transient overshoot the bulk
voltage may be pulled up to the peak value of mains
that is higher than the threshold of OVP1 and OVP2. In
this case the OVP1 and OVP2 are triggered in the
same time the IC will shut down the gate drive until bulk
voltage falls out of the two protection hysteresis, then
resume the gate drive again.
3.8.6 Bulk Voltage Monitor and Enable
Function
The IC monitors the bulk voltage through VSENSE pin
and output a TTL signal to enable PWM IC or control
inrush relay. During soft-start, once the bulk voltage is
higher than 95% rated value, pin VB_OK outputs a high
level. The threshold to trigger the low level is decided
by the pin VBTHL_EN voltage which can be adjustable
externally.
When pin VBTHL_EN is pulled down externally lower
than 0.5V, IC will enters into standby mode and most of
the function blocks are turned off. When the disable
signal is released the IC recovers by soft-start.
3.8.7 Boost Follower
The IC provides adjustable lower bulk voltage in case
of low line input and light output power. The low line
condition is determined when pin BOP voltage is less
than 2.3V. Pin BOFO is connected to PWM feedback
voltage through a voltage divider, representing the
output power. The light load condition is determined
when pin BOFO voltage is less than 0.5V. Once these
two conditions are met in the same time, a 20μA
current source is flowing out of pin VSENSE so that the
bulk voltage should be reduced to a lower level in order
Line
Filter
D
BRO1
D
BRO2
R
BRO1
R
BRO2
R
BRO3
90 ~ 270 Vac
C
BRO
BOP
C8b
C8a
R
S
Q
Q
Brownout
Latch
1.25 V
1V
Brownout
R
shunt
R
CS
Full-wave
rectifier
ISENSE
AO2
C5
200ns
SGND
G=-5
1V
I
in
PCL
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

ICE3PCS01GXUMA1

Mfr. #:
Buy ICE3PCS01GXUMA1
Manufacturer:
Infineon Technologies
Description:
Power Factor Correction - PFC STANDALONE PFC CTRLR IN CCM
Lifecycle:
New from this manufacturer.
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