CCM-PFC
ICE3PCS01G
Block Diagram
Version 3.0 7 03 April 2017
Table 1 Bill Of Material
Component Parameters
Rectifier Bridge GBU8J
C
E
100nF/X2/275V
L
Boost
750uH
Q
B
IPP60R199CP
D
BYP
MUR360
D
B
IDT04S60C
C
B
220µF/450V
D
BRO1...2
1N4007
R
BRO1...2
3.9MΩ
R
BRO3
130kΩ
C
BRO
3μF
R
shunt
30mΩ
C
isense
1nF
R
CS
50Ω
R
GATE
3.3Ω
R
FREQ
67kΩ
C
ICOMP
4.7nF/25V
R
BVS1...2
1.5MΩ
R
BVS3
18.85kΩ
R
BVS4...5
2MΩ
R
BVS6
23kΩ
R
VB1
330kΩ
R
VB2
200kΩ
C
VREF
100nF/25V
R
BOFO1...2
200kΩ
CCM-PFC
ICE3PCS01G
Functional Description
Version 3.0 8 03 April 2017
3 Functional
Description
3.1 General
The ICE3PCS01G is a 14-pins control IC for power
factor correction converters. It is suitable for wide range
line input applications from 85 to 265 VAC with overall
efficiency above 90%. The IC supports converters in
boost topology and it operates in continuous
conduction mode (CCM) with average current control.
The IC operates with a cascaded control; the inner
current loop and the outer voltage loop. The inner
current loop of the IC controls the sinusoidal profile for
the average input current. It uses the dependency of
the PWM duty cycle on the line input voltage to
determine the corresponding input current. This means
the average input current follows the input voltage as
long as the device operates in CCM. Under light load
condition, depending on the choke inductance, the
system may enter into discontinuous conduction mode
(DCM) resulting in a higher harmonics but still meeting
the Class D requirement of IEC 1000-3-2.
The outer voltage loop controls the output bulk voltage,
integrated digitally within the IC. Depending on the load
condition, internal PI compensation output is converted
to an appropriate DC voltage which controls the
amplitude of the average input current.
The IC is equipped with various protection features to
ensure safe operating condition for both the system
and device.
3.2 Power Supply
An internal under voltage lockout (UVLO) block
monitors the VCC power supply. As soon as it exceeds
12.0V and both voltages at pin 11 (VSENSE) >0.5V
and pin 9 (BOP) >1.25V, the IC begins operating its
gate drive and performs its startup as shown in Figure
3.
If VCC drops below 11V, the IC is off. The IC will then
be consuming typically 1.4mA, whereas consuming
6.7mA during normal operation
The IC can be turned off and forced into standby mode
by pulling down the voltage at pin 11 (VSENSE) below
0.5V or the voltage at pin 7 (VBTHL_EN) below 0.5V.
Figure 3 State of Operation respect to VCC
3.3 Start-up
During power up when the Vout is less than 95% of the
rated level, internal voltage loop output increases from
initial voltage under the soft-start control. This results in
a controlled linear increase of the input current from 0A
thus reducing the stress in the external components.
Once Vout has reached 95% of the rated level, the soft-
start control is released to achieve good regulation and
dynamic response and VB_OK pin outputs 5V
indicating PFC stage in normal operation.
3.4 Frequency Setting and External
Synchronization
The IC can provide external switching frequency
setting by an external resistor R
FREQ
and the online
synchronization by external pulse signal at FREQ pin.
3.4.1 Frequency Setting
The switching frequency of the PFC converter can be
set with an external resistor R
FREQ
at FREQ pin as
shown Figure 2. The pin voltage at V
FREQ
is typical 1V.
The corresponding capacitor for the oscillator is
integrated in the device and the R
FREQ
/frequency is
given in Figure 4. The recommended operating
frequency range is from 21kHz to 100kHz. As an
example, a R
FREQ
of 67kΩ at pin FREQ will set a
switching frequency F
SW
of 65kHz typically.
UVLO
OVP
configuration
within 50us
VREF rises to 5V with
100nF external cap.
within 200us
Bulk voltage rises to 95% rated valu e
within 200ms
V
BULK
V
CC
I
VCC
V
REF
VB_OK
20%
95%
100%
12V
5V
5V
1.4mA
5 mA
<6.7mA
with 1nF external cap. at gate dr ive pin
26V
3.5mA
Normal
operation
Standby mode
(V
VSENSE
< 0.5V or V
VBTHL
< 0.5V)
CCM-PFC
ICE3PCS01G
Functional Description
Version 3.0 9 03 April 2017
Figure 4 Frequency Versus R
FREQ
3.4.2 External Synchronization
The switching frequency can be synchronized to the
external pulse signal after 6 external pulses delay once
the voltage at the FREQ pin is higher than 2.5V. The
synchronization means two points. Firstly, the PFC
switching frequency is tracking the external pulse
signal frequency. Secondly, the falling edge of the PFC
signal is triggered by the rising edge of the external
pulse signal. Figure 5 shows the blocks of frequency
setting and synchronization. The external R
SYN
combined with R
FREQ
and the external diode D
SYN
can
ensure pin voltage to be kept between 1.0V (clamped
externally) and 5V (maximum pin voltage). If the
external pulse signal has disappeared longer than
108μs (typical) the switching frequency will be
synchronized to internal clock set by the external
resistor R
FREQ
.
Figure 5 Frequency Setting and
Synchronization
3.5 Voltage Loop
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V
OUT
. This loop is closed by the feedback
sensing voltage at VSENSE which is a resistive divider
tapping from V
OUT
. The pin VSENSE is the input of
sigma-delta ADC which has an internal reference of
2.5V and sampling rate of 3.55kHz (typical). The
voltage loop compensation is integrated digitally for
better dynamic response and saving design effort.
Figure 6 shows the important blocks of this voltage
loop.
Figure 6 Voltage Loop
3.5.1 Notch Filter
In the PFC converter, an averaged current through the
output diode of rectified sine waveform charges the
output capacitor and results in a ripple voltage at the
output capacitor with a frequency two times of the line
frequency. In this digital PFC, a notch filter is used to
remove the ripple of the sensed output voltage while
keeping the rest of the signal almost uninfluenced. In
this way, an accurate and fast output voltage regulation
without influence of the output voltage ripple is
achieved.
3.5.2 Voltage Loop Compensation
The Proportion-Integration (PI) compensation of the
voltage loop is integrated digitally inside the IC. The
digital data out of the PI compensator is converted to
analog voltage for current loop control.
R
FREQ
D
SYN
OTA 7
C9
R
SYN
FREQ
1. 0V
2 .5V /1. 25V
Syn . clock
I
OSC
SYN

ICE3PCS01GXUMA1

Mfr. #:
Manufacturer:
Infineon Technologies
Description:
Power Factor Correction - PFC STANDALONE PFC CTRLR IN CCM
Lifecycle:
New from this manufacturer.
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