74HC_HCT27_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 3 June 2013 6 of 15
NXP Semiconductors 74HC27-Q100; 74HCT27-Q100
Triple 3-input NOR gate
10. Dynamic characteristics
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
=C
PD
V
CC
2
f
i
N+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
Table 7. Dynamic characteristics
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ Max Max
(85 C)
Max
(125 C)
74HC27-Q100
t
pd
propagation delay nA, nB, nC to nY; see Figure 6
[1]
V
CC
= 2.0 V - 28 90 115 135 ns
V
CC
= 4.5 V - 10 18 23 27 ns
V
CC
= 5.0 V; C
L
=15pF - 8 - - - ns
V
CC
= 6.0 V - 8 15 20 23 ns
t
t
transition time see Figure 6
[2]
V
CC
= 2.0 V - 19 75 95 110 ns
V
CC
= 4.5 V - 7 15 19 22 ns
V
CC
= 6.0 V - 6 13 16 19 ns
C
PD
power dissipation
capacitance
per package; V
I
=GNDtoV
CC
[3]
-24- - -pF
74HCT27-Q100
t
pd
propagation delay nA, nB, nC to nY; see Figure 6
[1]
V
CC
= 4.5 V - 12 21 26 32 ns
V
CC
= 5.0 V; C
L
=15pF - 10 - - - ns
t
t
transition time V
CC
= 4.5 V; see Figure 6
[2]
- 7 15 19 22 ns
C
PD
power dissipation
capacitance
per package;
V
I
=GNDtoV
CC
1.5 V
[3]
-30- - -pF
74HC_HCT27_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 3 June 2013 7 of 15
NXP Semiconductors 74HC27-Q100; 74HCT27-Q100
Triple 3-input NOR gate
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. Input (nA, nB, nC) to output (nY) propagation delays and output transition times
001aag761
nA, nB, nC input
V
I
GND
V
OH
V
OL
nY output
t
THL
t
TLH
V
M
V
M
V
X
V
Y
t
PHL
t
PLH
Table 8. Measurement points
Type Input Output
V
M
V
M
V
X
V
Y
74HC27-Q100 0.5V
CC
0.5V
CC
0.1V
CC
0.9V
CC
74HCT27-Q100 1.3 V 1.3 V 0.1V
CC
0.9V
CC
74HC_HCT27_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 3 June 2013 8 of 15
NXP Semiconductors 74HC27-Q100; 74HCT27-Q100
Triple 3-input NOR gate
Test data is given in Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= Load capacitance including jig and probe capacitance.
R
L
= Load resistance.
S1 = Test selection switch
Fig 7. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
V
I
V
O
R
T
R
L
S1
C
L
open
G
Table 9. Test data
Type Input Load S1 position
V
I
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
74HC27-Q100 V
CC
6ns 15pF, 50 pF 1k open
74HCT27-Q100 3 V 6 ns 15 pF, 50 pF 1 k open

74HCT27BQ-Q100X

Mfr. #:
Manufacturer:
Nexperia
Description:
Logic Gates 74HCT27BQ-Q100/DHVQFN14/REEL 7
Lifecycle:
New from this manufacturer.
Delivery:
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