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ISL95311UIU10Z

P1-P3P4-P6P7-P9P10-P12
4
FN8084.2
August 13, 2015
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 15)
TYP
(Note 1)
MAX
(Note 15) UNIT
I
CC1
V
CC
Supply Current, Volatile
Write/read
f
SCL
= 400kHz; SDA = Open; (for I
2
C, active,
read, and volatile write states only)
1mA
I
CC2
V
CC
Supply Current, Nonvolatile
Write
f
SCL
= 400kHz; SDA = Open; (for I
2
C, active,
nonvolatile write states only)
3mA
I
SB
V
CC
Current, Standby V
CC
= +5.5V, I
2
C interface in standby state 5 µA
V
CC
= +3.6V, I
2
C interface in standby state 2 µA
I
V+
V+ Bias Current V+ = 13.2V, V
CC
= +5.5V 1 µA
I
LkgDig
Leakage Current, at Pins SDA, SCL,
A0, and A1 Pins
Voltage at pin from GND to V
CC
-10 10 µA
t
DCP
DCP Wiper Response Time SCL falling edge of last bit of DCP data byte to
wiper change
1µs
Vpor Power-On Recall Voltage V
CC
range at which memory recall occurs 1.5 1.8 2.6 V
V
CC
Ramp V
CC
Ramp Rate 0.2 V/ms
t
D
Power-Up Delay V
CC
above Vpor, to DCP initial value register
recall completed, and I
2
C Interface in standby
state
3ms
EEPROM SPECS
EEPROM Endurance 200,000 Cycles
EEPROM Retention Temperature +75°C 50 Years
SERIAL INTERFACE SPECS
V
IL
A0, A1, SDA, and SCL Input Buffer
LOW Voltage
-0.3 0.3*
V
CC
V
V
IH
A0, A1, SDA, and SCL Input Buffer
HIGH Voltage
0.7*
V
CC
V
CC
+
0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis 0.05*
V
CC
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4V
Cpin A0, A1, SDA, and SCL Pin
Capacitance
10 pF
f
SCL
SCL Frequency 400 kHz
t
IN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50 ns
t
AA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window
900 ns
t
BUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition
1300 ns
t
LOW
Clock LOW Time Measured at the 30% of V
CC
crossing 1300 ns
t
HIGH
Clock HIGH Time Measured at the 70% of V
CC
crossing 600 ns
t
SU:STA
START Condition Set-up Time SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
600 ns
t
HD:STA
START Condition Hold Time From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
600 ns
t
SU:DAT
Input Data Set-up Time From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
100 ns
ISL95311
5
FN8084.2
August 13, 2015
t
HD:DAT
Input Data Hold Time From SCL rising edge crossing 30% of V
CC
to
SDA entering the 30% to 70% of V
CC
window
0ns
t
SU:STO
STOP Condition Set-up time From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
600 ns
t
HD:STO
STOP Condition Hold Time From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
600 ns
t
DH
Output Data Hold Time From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window
0ns
t
R
(Note 14)
SDA and SCL Rise Time From 30% to 70% of V
CC
20 +
0.1 * Cb
250 ns
t
F
(Note 14)
SDA and SCL Fall Time From 70% to 30% of V
CC
20 +
0.1 * Cb
250 ns
Cb
(Note 14)
Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF
Rpu
(Note 14)
SDA and SCL Bus Pull-Up Resistor
Off-Chip
Maximum is determined by t
R
and t
F
,
For Cb = 400pF, max is about 2k~2.5k.
For Cb = 40pF, max is about 15k~20k.
1k
t
WP
(Notes 13)
Non-Volatile Write Cycle Time 12 20 ms
t
SU:A
A0, A1 Set-up Time Before START condition 600 ns
t
HD:A
A0, A1 Hold Time After STOP condition 600 ns
NOTES:
1. Typical values are for T
A
= +25°C and 3.3V supply voltage.
2. LSB: [V(R
W
)
127
– V(R
W
)
0
]/127. V(R
W
)
127
and V(R
W
)
0
are V(R
W
) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(R
W
)
0
/LSB.
4. FS error = [V(R
W
)
127
– V+]/LSB.
5. DNL = [V(R
W
)
i
– V(R
W
)
i-1
]/LSB-1, for i = 1 to 127. i is the DCP register setting.
6. INL = V(R
W
)
i
– (i • LSB – V(R
W
)
0
) for i = 1 to 127.
7.
for i = 16 to 120 decimal, T = -40°C to 85°C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper
voltage over the temperature range.
8. MI =
|R
127
– R
0
|/127. R
127
and R
0
are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.
9. Roffset = R
0
/MI, when measuring between R
W
and R
L
.
Roffset = R
127
/MI, when measuring between R
W
and R
H
.
10. RDNL = (R
i
– R
i-1
)/MI, for i = 16 to 127.
11. RINL = [R
i
– (MI • i) – R
0
]/MI, for i = 16 to 127.
12.
for i = 16 to 127, T = -40°C to +85°C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the
temperature range.
13. t
WP
is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid
STOP condition at the end of a Write sequence of a I
2
C serial interface Write operation, to the end of the self-timed internal non-volatile write
cycle.
14. Recommended operating limits and are not production tested.
15. Parts are 100% tested at +85°C. Over temperature limits established by characterization and are not production tested.
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 15)
TYP
(Note 1)
MAX
(Note 15) UNIT
TC
V
Max V RW
i
Min V RW
i
–
Max V RW
i
Min V RW
i
+2
----------------------------------------------------------------------------------------------
10
6
125°C
-----------------
=
TC
R
Max RiMin Ri–
Max RiMin Ri+2
----------------------------------------------------------------
10
6
125°C
-----------------
=
ISL95311
6
FN8084.2
August 13, 2015
SDA vs SCL Timing
A0, A1 Pin Timing
Pin Descriptions
Potentiometer Pins
R
H
and R
L
R
L
and R
H
are referenced to the relative position of the
wiper and not the voltage potential on the terminals. With
WR set to 127, the wiper will be closest to R
H
, and with the
WR set to 00, the wiper is closest to R
L
.
R
W
R
W
is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for the
I
2
C interface. It receives device address, operation code,
wiper register address and data from a I
2
C external master
device at the rising edge of the serial clock SCL, and it shifts
out data after each falling edge of the serial clock SCL.
SDA requires an external pull-up resistor, since it’s an open
drain input/output.
SERIAL CLOCK (SCL)
This input is the serial clock of the I
2
C serial interface.
SCL requires an external pull-up resistor, since it’s an open
drain input.
DEVICE ADDRESS (A1–A0)
The Address inputs are used to set the least significant 2 bits
of the 8-bit I
2
C interface slave address. A match in the slave
address serial data stream must be made with the Address
input pins in order to initiate communication with the
ISL95311. A maximum of four ISL95311 devices may occupy
the I
2
C serial bus.
Principles of Operation
The ISL95311 is an integrated circuit incorporating one DCP
with their associated register, non-volatile memory, and a
I
2
C serial interface providing direct communication between
a host and the potentiometers and memory. The resistor
array is comprised of 127 individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch between that point and the wiper.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
t
HD:A
SCL
SDA IN
A0, A1
t
SU:A
CLK 1
START
STOP
ISL95311
P1-P3P4-P6P7-P9P10-P12

ISL95311UIU10Z

Mfr. #:
Buy ISL95311UIU10Z
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs I2C 128 POSITION NON VOL DCP 50 KOHMS
Lifecycle:
New from this manufacturer.
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