7
FN8084.2
August 13, 2015
On applying power to the ISL95311, the V
CC
supply should
have a monotonic ramp to the specified operating voltage. It
is important that once V
CC
reaches 1V that it increases to at
least 2.5V in less than 7.5ms (0.2V/ms). The ramp rate
before and after these thresholds is not important.
V
CC
must be applied prior to, or simultaneously, with V+.
Under no condition should V+ be applied without V
CC
. While
the sequence of applying V+ and V
CC
to the ISL95311 does
not affect the proper recall of the wiper position, applying V+
before V
CC
powers the electronic switches of the DCP
before the electronic switch control signals are applied. This
can result in multiple electronic switches being turned on,
which could load the power supply and cause brief,
unexpected potentiometer wiper settings.
To prevent unknown wiper positions on the ISL95311 on
power-down, it is recommended that V+ turn off before or
simultaneously with V
CC
. If V+ remains on after V
CC
turns
off, the wiper position can remain unchanged from its
previous setting or it can go to an undefined state.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
pins). The R
W
pin is connected to
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal within the DCP is controlled by a 7-bit volatile Wiper
Register (WR). When the WR contains all zeroes (00h), the
wiper terminal (R
W
) is closest to its “Low” terminal (R
L
).
When the WR contains all ones (7Fh), the wiper terminal
(R
W
) is closest to its “High” terminal (R
H
). As the value of the
WR increases from all zeroes (00h) to all ones (7Fh), the
wiper moves monotonically from the position closest to R
L
to
the position closest to R
H
. At the same time, the resistance
between R
W
and R
L
increases monotonically, while the
resistance between R
H
and R
W
decreases monotonically.
While the ISL95311 is being powered up, the WR is reset to
20h (64 decimal), which locates the R
W
at the center between
R
L
and R
H
. Soon after the power supply voltage becomes
large enough for reliable non-volatile memory reading, the
ISL95311 reads the value stored on a non-volatile Initial Value
Register (IVR) and loads it into the WR.
The WR and IVR can be read from or written to directly using
the I
2
C serial interface as described in the following
sections.
Memory Description
The ISL95311 contains 1 non-volatile byte know as the Initial
Value Register (IVR). It is accessed by the I
2
C interface
operations with Address 00h. The IVR contains the value
which is loaded into the Volatile Wiper Register (WR) at
power-up.
The volatile WR, and the non-volatile IVR of a DCP are
accessed with the same address.
The Access Control Register (ACR) determines which word
at address 00h is accessed (IVR or WR). The volatile ACR
must be set as follows:
When the ACR is all zeroes, which is the default at power-up:
• A read operation to address 0 outputs the value of the
non-volatile IVR.
• A write operation to address 0 writes the identical values
to the WR and IVR of the DCP.
• When the ACR is 80h:
• A read operation to address 0 outputs the value of the
volatile WR.
• A write operation to address 0 only writes to the
volatile WR.
It is not possible to write to an IVR without writing the same
value to its WR.
00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be
written to address 2.
The ISL95311 is pre-programmed with 40h in the IVR.
I
2
C Serial Interface
The ISL95311 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL95311
operates as a slave device in all applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 1). On power-up of the ISL95311, the SDA pin is in
the input mode.
All I
2
C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
TABLE 1. MEMORY MAP
ADDRESS NON-VOLATILE VOLATILE
2-ACR
1 Reserved
0IVRWR
WR: Wiper Register, IVR: Initial value Register.
ISL95311
