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PI6C48543LE

P1-P3P4-P6
1
PS8771B 10/02/08
PI6C48543
Block Diagram
Features
• Maximum operation frequency: 800 MHz
• 4 pair of differential LVDS outputs
• Selectable differential CLK and PCLK inputs
• CLK,
n
CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL
and HCSL input level
• PCLK, nPCLK pair supports LVPECL, CML and SSTL
input level
• Output Skew: 40ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 2.2ns (maximum)
• 3.3V power supply
• Pin-to-pin compatible to ICS8543
• Operating Temperature: -40
o
C to 85
o
C
• Packaging (Pb-free & Green):
-20-pin TSSOP (L)
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Description
The PI6C48543 is a high-performance low-skew LVDS fanout
buffer. PI6C48543 features two selectable differential inputs and
translates to four LVDS outputs. The inputs can also be confi gured
to single-ended with external resistor bias circuit. The CLK input
accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals,
and PCLK input accepts LVPECL or SSTL or CML signals. The
outputs are synchronized with input clock during asynchronous
assertion/deassertion of CLK_EN pin. PI6C48543 is ideal for
differential to LVDS translations and/or LVDS clock distribution.
Typical clock translation and distribution applications are data-
communications and telecommunications.
Pin Diagram
Q
0
n
Q
0
V
CC
Q
1
n
Q
1
Q
2
n
Q
2
GND
Q
3
n
Q
3
GND
CLK_EN
CLK_SEL
CLK
n
CLK
PCLK
n
PCLK
OE
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK_EN
CLK
n
CLK
PCLK
n
PCLK
CLK_SEL
OE
Q
0
n
Q
0
Q
1
n
Q
1
Q
2
n
Q
2
Q
3
n
Q
3
0
1
D
LE
Q
08-0247
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
2
PS8771B 10/02/08
Pin Description
Name Pin # Type Description
GND 1, 9, 13 P Connect to Ground
CLK_EN 2 I_PU
Synchronized clock enable. When high, clock outputs follow clock input. When low, Q
x
outputs are forced low,
n
Q
x
outputs are forced high. LVCMOS/LVTTL level with 80kΩ pull up.
CLK_
SEL
3 I_PD
Clock select input. When high, selects CLK
1
input. When low, selects CLK
0
input. LVCMOS/
LVTTL level with 80kΩ pull down.
CLK 4 I_PD Non-inverting differential clock input
n
CLK 5 I_PU Inverting differential clock input
PCLK 6 I_PD Non-inverting differential clock input
n
PCLK 7 I_PU Inverting differential clock input
OE 8 I_PU Output Enable, Controls outputs Q
0
,
n
Q
0
through Q
3
,
n
Q
3
V
CC
10, 18 P Connect to 3.3V.
Q
3
,
n
Q
3
11, 12 O Differential output pair, LVDS interface level.
Q
2
,
n
Q
2
14, 15 O Differential output pair, LVDS interface level.
Q
1
,
n
Q
1
16, 17 O Differential output pair, LVDS interface level.
Q
0
,
n
Q
19, 20 O Differential output pair, LVDS interface level.
Notes:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up
Pin Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units
C
IN
Input Capacitance 6 pF
R_pullup Input Pullup Resistance 80
kΩ
R_pulldown Input Pulldown Resistance 80
Control Input Function Table
Inputs Outputs
OE CLK_EN CLK_SEL Selected Source Q
0
:Q
3n
Q
0
:
n
Q
3
1 0 0 CLK,
n
CLK Diasbled: Low Diasbled: High
1 0 1 PCLK,
n
PCLK Disabled: Low Disabled: High
1 1 0 CLK,
n
CLK Enabled Enabled
1 1 1 PCLK,
n
PCLK Enabled Enabled
0 x x Hi-Z Hi-Z
Notes:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
08-0247
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
3
PS8771B 10/02/08
Figure 1. CLK_EN Timing Diagram
Clock Input Function Table (See Figure 2)
Inputs Outputs
Input to Output Mode Polarity
CLK or PCLK
n
CLK or
n
PCLK Q
0
:Q
3n
Q
0
:
n
Q
3
0 1 LOW HIGH Differential to Differential None Inverting
1 0 HIGH LOW Differential to Differential None Inverting
0 Biased; V
IN
= V
CC
/2 LOW HIGH Single Ended to Differential None Inverting
1 Biased; V
IN
= V
CC
/2 HIGH LOW Single Ended to Differential None Inverting
Biased; V
IN
=
Vcc/2
0 HIGH LOW Single Ended to Differential Inverting
Biased; V
IN
=
V
CC
/2
1 LOW HIGH Single Ended to Differential Inverting
Absolute Maximum Ratings
Symbol Parameter Conditions Min. Typ. Max. Units
V
CC
Supply voltage Referenced to GND 4.6
VV
IN
Input voltage Referenced to GND -0.5 V
CC
+0.5V
V
OUT
Output voltage Referenced to GND -0.5 V
CC
+0.5V
T
STG
Storage temperature -65 150
o
C
Notes:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci
fi cations only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of
the specifi cations is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
Disabled
Enabled
08-0247
P1-P3P4-P6

PI6C48543LE

Mfr. #:
Buy PI6C48543LE
Manufacturer:
Diodes Incorporated
Description:
Clock Buffer Fanout Buffer 3.3V
Lifecycle:
New from this manufacturer.
Delivery:
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