AD5801 Preliminary Technical Data
Rev. 0 | Page 10 of 13
filtering when combined with the piezo element. The AD5801
Slope Mode effectively allows the user to control the rise and
fall times of the drive waveform by using predetermined PWM
patterns and driving these patterns into an LC load.
The AD5801 have several default patterns, which after filtering
by the addition of a suitable inductor in series with the
capacitance of the piezo load, produces a rhombic or triangular
waveform at the piezo element. The principle on which this
mode works is that the pattern density increases linearly and
then decreases linearly from:
X
X
X
→
1
Where: X is 8, 9, 10 or 11
The default patterns are register selected and allow the user to
effectively control the rise and fall times of the waveforms
across the piezo motor. The AD5801 PWM Slope Mode pattern
causes the waveform across the piezo element to ramp from
GND to an output high level defined by the supply voltage
connected to the PWR_DRIVESTAGE pin. The period set in
the PWMPERIOD register defines the high and low time within
one period. For example:
if selected X value = 10
and PWMPERIOD = 254
Then the number of counter periods, as defined in the
PWNUNIT register that are on the top and bottom of the
resultant waveform are calculated with the following Formula:
Number of Periods =
2
2
2
×− XPWMPERIOD
In the case where X = 10
Number of Periods =
26
2
210254
2
=
×−
So there are 26 counter periods on top and bottom of the
resultant rhombic waveform. Figure 5 illustrates the AD5800
driving a default PWM Slope Mode pattern through a series
inductor and into the piezo load, and the resultant waveforms.
G G
AD5800 Slope Mode Pattern
esultant
a
eform across Piezo Element
ue to Filteri n
Figure 5. AD5801 Slope Mode Pattern and resulting filtered
waveform across the piezo motor.
The primary advantage of using the AD5801 in Slope Mode is
that the rise and fall times of the driving waveform are
controlled, and therefore the power surges associated when
driving the piezo element with a square wave at its resonant
frequency are eliminated.
Clock Generation
The AD5801 offers the user the choice of two master clock
sources, an internal clock generated from an integrated VCO, or
an external clock applied through the EXCLK pin. The external
reference clock is provided by the baseband processor in the
host system, and can be either a DC coupled square wave or an
AC coupled sine wave. In either case the clock may have been
RC filtered. The clock may be either a free running system clock
or dedicated camera module clock, which may be enabled and
disabled by the host. The AD5801 has a highly accurate PLL
based clock generator which accepts an accurate and stable
multiple of the external clock (4.8MHz or 9.6MHz), and
multiplies its frequency to the master clock of 19.44MHz
required by the AD5801.
The AD5801 also has the option of using an integrated clock
generator. The MCLKCONTROL Register allows the user to
select either the external or integrated clock source, select. If an
external clock is used then the MCLKCONTROL Register
allows the user to set the AD5801 EXTCLK pin to accept an
AC-coupled or DC-coupled clock, and also allows the user to
select the master clock frequency supplied, or to bypass the PLL
if the master clock is 19.44MHz. The internal clock is generated
using a 2% accurate VCO.
ADC and Lens Position Sensing
The AD5801 has an integrated on board 12 bit ADC. The ADC
contains an on-chip track and hold amplifier, a successive
approximation A/D converter. Clocking for the A/D is provided
using a divided down ratio of the integrated or host master
reference clock.
