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AD5801BCPZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P13
AD5801 Preliminary Technical Data
Rev. 0 | Page 4 of 13
BIAS
BIASRES
Bias reference Voltage 1.275 V
Output Current range Current to POSSENSAF-Z 4 10 19 mA
Output Current Accuracy 2.5 %
External Resistor
4
R
term
5.1 k Ω
External Resistor Tolerance -1 1 %
Shutter Controls
SOUT1-SOUT3
Output Current Range 130 200 mA
Accuracy
5
±5 %
Step Size 10 mA
Shutter Strobe
STROBE
Strobe Time 5 35 ms
Input High Voltage V
IH
1.17 V
Input Low Voltage V
IL
0.63 V
Low Drop Out Regulator
6
LDO_ACT
Programmable Output Voltage Range 2.8 3.3 V
Output Current Drive Capability 200 mA
Accuracy
5
±3 %
Programmable Output Voltage Level 1 2.8 V
Programmable Output Voltage Level 2 2.9 V
Programmable Output Voltage Level 3 3.0 V
Programmable Output Voltage Level 4 3.3 V
LDO Compensation Capacitor 10 20 µF
External Clock
7
EXTCLK
Clock Frequency Range 4.8 19.44 MHz
Internal Clock
7
INTCLK
Clock Frequency 19.44 MHz
I2C Interface
8
SDA, SCL Input High Voltage V
IH
1.3 1.8 VAUX V
SDA, SCL Input Low Voltage V
IL
0 0.4 V
Glitch Rejection 50 ns
ShutDown/Standby/RESET
9
XSHUTDOWN
XSD High Level Input voltage 1.17 V
XSD Low Level Input voltage 0.63 V
Minimum Valid Shutdown period 100 ns
Min Time Between Successive XSD Pulses TBD ns
Power Supply
VBATT Battery Supply 2.8 4.5 V
Currrent Consumption in Active Mode TBD mA
Current on VBATT TBD mA
VAUX Digital Supply 2.5 VBATT V
Current on VAUX TBD
µA
PWR_DRIVESTAGE FA-FB Drivers 2.5 5 V
SHUTTER_VBATT Shutter Supply 2.5 5 V
PWR_DRIVERS
FC, FD, ZA-ZD
Drivers
2.5 5 V
1
Temperature range is as follows: B Version: −40°C to +70°C
1
See Figure 3 for timing programmability details.
3
The conversion time of 160µs is due to averaging of four measurements taken by the ADC,. The averaging feature can be disabled and the conversion time is then
40µs.
4
An external precision resistor is required to establish bias currents and voltages.
5
This is the accuracy over the entire temperature range.
Preliminary Technical Data AD5801
Rev. 0 | Page 5 of 13
6
A minimum 10µF capacitor is required for LDO_ACT. A 4.7 µF is required at the pin LDO2_COMP.
7
The AD5801 can be programmed for use with an external or internal clock.
8
See Table 3 and Figure 2 for I2C timing specifications.
9
Bringing XSHUTDOWN low disables the I2C interface, on a low to high transition there is a reset on the AD5801.
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters Rating
VCC to GND TBD
Digital Inputs −0.3 V to (VDD + 0.3 V)
Voltage on Analog Inputs −0.3 V to (VCC + 0.3 V)
DRPWR pins to GND -0.3V to TBD
FOUT pins to GND -0.3V to TBD
ZOUT pins to GND -0.3V to TBD
Maximum Voltage between GND pins
1
±0.3V
Operating Temperature Range −30°C to +70°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
32-Lead LFCSP
θ
JA
Thermal Impedance 32°C/W
Lead Temperature, Soldering (10 s) 300°C
1
This is the maximum allowable voltage between the various
GND pins on the AD5801.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5801 Preliminary Technical Data
Rev. 0 | Page 6 of 13
Table 3. I
2
C Serial Interface
Parameter
1
Limit at T
MIN
, T
MAX
Unit Description
F
SCL
400 kHz max SCL clock frequency
t
1
2.5 µs min SCL cycle time
t
2
0.6 µs min t
HIGH
, SCL high time
t
3
1.3 µs min t
LOW
, SCL low time
t
4
0.6 µs min t
HD
,
STA
, start/repeated start condition hold time
t
5
100 ns min t
SU
,
DAT
, data setup time
t
6
2
0.9 µs max t
HD
,
DAT
data hold time
0 µs min t
HD
,
DAT
data hold time
t
7
0.6 µs min t
SU
,
STA
setup time for repeated start
t
8
0.6 µs min t
SU
,
STO
stop condition setup time
t
9
1.3 µs min t
BUF
, bus free time between a stop and a start condition
t
10
300 ns max t
F
, fall time of SDA when transmitting
0 ns min t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
11
300 ns max t
F
, fall time of SDA when transmitting
0 ns min t
F
, fall time of SDA when receiving (CMOS compatible)
300 ns max t
F
, fall time of SCL and SDA when receiving
20 + 0.1 C
B
ns min t
F
, fall time of SCL and SDA when transmitting
C
B
3
400 pF max Capacitive load for each bus line
1
See 2.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
MIN of the SCL signal)
to bridge the undefined region of SCL’s falling edge.
3
C
B
is the total capacitance of one bus line in pF; t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
03773-0-007
SCL
SD
A
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
9
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
8
t
1
Figure2.. I
2
C Interface Timing Diagram
Block Diagram
P1-P3P4-P6P7-P9P10-P12P13-P13

AD5801BCPZ-REEL7

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Analog Devices Inc.
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IC LENS DRIVER 9-CHAN 32-LFCSP
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