NCP1256
www.onsemi.com
19
The double hiccup is operating regardless of the
brown−out level. However, when the internal comparator
toggles indicating that the controller recovers from a
brown−out situation (the input line was ok, then too low and
back again to normal), the double hiccup is interrupted and
the controller re−starts to the next available V
cc
peak.
Figure 42 displays the resulting waveform: the controller is
protecting the converter against an overload. The mains
suddenly went down, and then back again at a normal level.
Right at this moment, the double hiccup logic receives a
reset signal and ignores the next hiccup to immediately
initiate a re−start signal.
8.8 V
18 V
()
cc
Vt
()
DRV
Vt
Restart
Brownout
recovery
1
2
1
2
1
BONOK
BOK BOK
Figure 42. The hiccup latch is reset when a brown−out transition is detected to shorten the re−start time
Latched Short Circuit Protection with Pre Short
In some applications, the controller must be fully latched
in case of an output short circuit presence. In that case, you
would select options A in the controller list. When the error
flag is asserted, meaning the controller is asked to deliver its
full peak current, upon timer completion, the controller
latches off: all pulses are immediately stopped and V
cc
hiccups between the two levels, VCC
ON
and VCC
(min)
.
However, in presence of a small V
cc
capacitor, it can very
well be the case where the stored energy does not give
enough time to let the timer elapse before V
cc
touches
UVLO. When this happens, the latch is not acknowledged
since the timer countdown has been prematurely aborted. To
avoid this problem, NCP1256 (with latched−OCP option)
combines the error flag assertion together with the UVLO
flag to confirm a pre−short situation: upon start up, as
maximum power is asked to increase V
out
, the error flag is
temporarily raised until regulation is met. If during the time
the flag is raised an UVLO event is detected, the part latches
off immediately. When latched, V
cc
hiccups between the
two levels, VCC
ON
and VCC
(min)
until a reset occurs
(Brown−out event or V
cc
cycled down below VCC
reset
). In
normal operation, if a UVLO event is detected for any
reason while the error flag is not asserted, the controller will
naturally resume operations in a double hiccup mode.
Details of this behavior are given in Figure 43.
NCP1256
www.onsemi.com
20
Newsequence
UVLO
AND
err. flag
latched
()
cc
vt
()
DRV
vt
Errorflag
0
1
1
resumed
glitch
VCC
ON
VCC
(min)
t
t
t
Figure 43. In case a UVLO event is sensed while the error flag is asserted, full latch occurs
UVLO latch is made available solely during the start−up
sequence. When the power supply starts−up, the loop is open
and asks for maximum peak current. The internal fault flag
is armed and the fault timer counts down. If an UVLO event
occurs during this time, the part immediately latches off. If
no UVLO occurs, once the output voltage has reached
regulation, the internal error flag is released and the latch
authorizing UVLO detections is reset: any new UVLO
events will simply be ignored. In the latched−OCP version,
UVLO test is available at the first power up, when
recovering from a brown−out episode or while the part
operates in hiccup mode.
2
5
6
S
R
Q
Q
3
4
1
VCCon ? 1 : 0
Error flag down ? 1 : 0
UVLO ? 1 : 0
latch
error
VCC
ON
Latched is armed at power up
Figure 44. In case a UVLO event is sensed while the
error flag is asserted, full latch occurs. UVLO
observation disappears if regulation is successful
after the first start−up sequence.
NCP1256
www.onsemi.com
21
Frequency Foldback
The reduction of no−load standby power associated with
the need for improving the efficiency, requires a change in
the traditional fixed−frequency type of operation. This
controller implements a switching frequency foldback when
the feedback voltage passes below a certain level, V
fold
, set
at 1.5 V. At this point, the oscillator turns into a
Voltage−Controlled Oscillator (VCO) and reduces
switching frequency down to a feedback voltage of 1.2 V
where switching frequency is 26 kHz typically. Below 1.2 V,
the frequency is fixed and cannot go further down. The peak
current setpoint is free to follow the feedback voltage from
2.4 V (full power) down to 0.75 V. At 0.75 V, as both
frequency and peak current are frozen (250 mV or 31% of
the maximum 0.8−V setpoint) the only way to further reduce
the transmitted power is to enter skip cycle and chop the
switching pattern. This is what happens when the feedback
voltage drops below 0.6 V typically. Figure 45 depicts the
adopted scheme for the part.
F
sw
V
FB
V
CS
V
FB
65 kHz
26 kHz
0.6 V
V
fold
2.4 V
V
fold
3.2 V
0.8 V
[0.5 V
FB
V
freeze
[0.25 V
0.75 V 1.5 V
1.5 V
max
min
min
V
fold,end
Frequency Peak current setpoint
4 V
V
skip
0.6 V
1.2 V
Figure 45. By observing the voltage on the feedback pin, the controller reduces its
switching frequency for an improved performance at light load
V
FB
(V)
4.0
2.4
Peak current
is clamped
F
sw
is fixed
65 kHz
1.5
0.6
t
0 dutyratio
F
sw
decreases
65 kHz
0.75
Peak current
is frozen
I
peak
min
I
peak
max
Peak current
can change
1.2
26 kHz
Open loop
Figure 46. Another look at the relationship between feeback and
current setpoint while in frequency reduction mode.

NCP1256ESN65T1G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers NCP1256E 65KHZ
Lifecycle:
New from this manufacturer.
Delivery:
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