NCN6010
http://onsemi.com
15
The layout of the PCB is a key parameter to avoid the
voltage spikes that could pollute the rest of the system.
Figure 16 represents a typical printed circuit lay out, based
on the schematic diagram given in Figure 14, highlighting
the large ground plane used in this engineering tool.
Obviously, a GSM application will use much less area, but
cares must be observed to locate the capacitors as close as
possible to the integrated circuit associated pins.
Capacitors C1, C2, C3, C4 and C5 are ceramic, X7R, 10 V,
surface mount.
Figure 15. Engineering Test Board Silk Layer
Figure 16. Engineering Test Board Top Layer
