NCV4276B
http://onsemi.com
10
TYPICAL PERFORMANCE CHARACTERISTICS − Adjustable Version
0
0.2
0.4
1.6
0 10203040 60
I
Q
, OUTPUT CURRENT (mA)
T
J
= 25°C
0
100
200
300
400
500
600
0 50 100 150 350 400
I
Q
, OUTPUT CURRENT (mA)
V
DR
, DROPOUT VOLTAGE (mV)
T
J
= 25°C
V
I
= 13.5 V
Figure 24. Dropout Voltage vs. Output Current,
Regulator Set at 5.0 V, Adjustable Version
0.6
0.8
1.0
1.2
1.4
50
200 250 300
T
J
= 125°C
0
100
200
300
400
500
800
0 1020304050
V
I
, INPUT VOLTAGE (V)
I
Q
, OUTPUT CURRENT (mA)
T
J
= 25°C
V
Q
= 0 V
Figure 25. Maximum Output Current vs.
Input Voltage, Adjustable Version
600
700
0
10
20
30
40
50
60
0 100 200 300 400
I
Q
, OUTPUT CURRENT (mA)
I
q
, CURRENT CONSUMPTION (mA)
T
J
= 25°C
V
I
= 13.5 V
Figure 26. Current Consumption vs.
Output Current (High Load), Adjustable Version
500 600
Figure 27. Current Consumption vs. Output
Current (Low Load), Adjustable Version
I
q
, CURRENT CONSUMPTION (mA)
NCV4276B
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11
Circuit Description
The NCV4276B is an integrated low dropout regulator
that provides a regulated voltage at 400 mA to the output.
It is enabled with an input to the inhibit pin. The regulator
voltage is provided by a PNP pass transistor controlled by
an error amplifier with a bandgap reference, which gives it
the lowest possible dropout voltage. The output current
capability is 400 mA, and the base drive quiescent current
is controlled to prevent oversaturation when the input
voltage is low or when the output is overloaded. The
regulator is protected by both current limit and thermal
shutdown. Thermal shutdown occurs above 150°C to
protect the IC during overloads and extreme ambient
temperatures.
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (V
Q
) and drives the base of a
PNP series pass transistor via a buffer. The reference is a
bandgap design to give it a temperature-stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Oversaturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized. See Figure 4, Test Circuit, for
circuit element nomenclature illustration.
Regulator Stability Considerations
The input capacitors (C
I1
and C
I2
) are necessary to
stabilize the input impedance to avoid voltage line
influences. Using a resistor of approximately 1.0 W in
series with C
I2
can stop potential oscillations caused by
stray inductance and capacitance.
The output capacitor helps determine three main
characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25°C to −40°C), both the
value and ESR of the capacitor will vary considerably. The
capacitor manufacturers data sheet usually provides this
information.
The value for the output capacitor C
Q
, shown in Figure 3,
should work for most applications; see also Figures 5 to 7
for output stability at various load and Output Capacitor
ESR conditions. Stable region of ESR in Figures 5 to 7
shows ESR values at which the LDO output voltage does
not have any permanent oscillations at any dynamic
changes of output load current. Marginal ESR is the value
at which the output voltage waving is fully damped during
four periods after the load change and no oscillation is
further observable.
ESR characteristics were measured with ceramic
capacitors and additional series resistors to emulate ESR.
Low duty cycle pulse load current technique has been used
to maintain junction temperature close to ambient
temperature.
Minimum ESR for C
Q
=22mF is native ESR of ceramic
capacitor with which the fixed output voltage devices are
performing stable. Murata ceramic capacitors were used,
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210),
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206).
Calculating Bypass Capacitor
If usage of low ESR ceramic capacitors is demand in case
of Adjustable Regulator, connect the bypass capacitor C
b
between Voltage Adjust pin and Q pin according to
Applications circuit at Figure 4.
Parallel combination of bypass capacitor C
b
with the
feedback resistor R
1
contributes in the device transfer
function as an additional zero and affects the device loop
stability, therefore its value must be optimized. Attention
to the Output Capacitor value and its ESR must be paid. See
also Stability in High Speed Linear LDO Regulators
Application Note, AND8037/D for more information.
Optimal value of bypass capacitor is given by following
expression
C
b
+
1
2 p f
z
R
1
@ (F)
(eq. 1)
where
R
1
= the upper feedback resistor
f
z
= the frequency of the zero added into the device
transfer function by R
1
and C
b
external components.
Set the R
1
resistor according to output voltage
requirement. Chose the f
z
with regard on the output
capacitance C
Q
, refer to the table below.
C
Q
(mF) 10 22 47 100
f
z
Range (kHz) 20 - 50 14 - 35 10 - 20 7 – 14
Ceramic capacitors and its part numbers listed bellow
have been used as low ESR output capacitors C
Q
from the
table above to define the frequency ranges of additional
zero required for stability.
GRM31CR71C106KAC7 (10 mF, 16 V, X7R, 1206)
GRM32ER71C226KE18 (22 mF, 16 V, X7R, 1210)
GRM32ER61C476ME15 (47 mF, 16 V, X5R, 1210)
GRM32ER60J107ME20 (100 mF, 6.3 V, X5R, 1210)
Inhibit Input
The inhibit pin is used to turn the regulator on or off. By
holding the pin down to a voltage less than 1.8 V, the output
of the regulator will be turned off. When the voltage on the
Inhibit pin is greater than 2.8 V, the output of the regulator
will be enabled to power its output to the regulated output
voltage. The inhibit pin may be connected directly to the
input pin to give constant enable to the output regulator.
Setting the Output Voltage (Adjustable Version)
The output voltage range of the adjustable version can be
set between 2.5 V and 20 V. This is accomplished with an
external resistor divider feeding back the voltage to the IC
NCV4276B
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12
back to the error amplifier by the voltage adjust pin VA.
The internal reference voltage is set to a temperature stable
reference of 2.5 V.
The output voltage is calculated from the following
formula. Ignoring the bias current into the VA pin:
V
Q
+ [(R1 ) R2) * V
ref
] ń R2
(eq. 2)
Use R2 < 50 k to avoid significant voltage output errors
due to VA bias current.
Connecting VA directly to Q without R1 and R2 creates
an output voltage of 2.5 V.
Designers should consider the tolerance of R1 and R2
during the design phase.
The input voltage range for operation (pin 1) of the
adjustable version is between (V
Q
+ 0.5 V) and 40 V.
Internal bias requirements dictate a minimum input voltage
of 4.5 V. The dropout voltage for output voltages less than
4.0 V is (4.5 V − V
Q
).
Calculating Power Dissipation
in a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 28) is:
P
D(max)
+ [V
I(max)
* V
Q(min)
]I
Q(max)
)
) V
I(max)
I
q
(eq. 3)
where:
V
I(max)
is the maximum input voltage,
V
Q(min)
is the minimum output voltage,
I
Q(max)
is the maximum output current for the
application,
I
q
is the quiescent current the regulator
consumes at I
Q(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
q
JA
can be calculated:
R
qJA
+
150
o
C *
T
A
P
D
(eq. 4)
The value of R
q
JA
can then be compared with those in the
package section of the data sheet. Those packages with
R
q
JA
less than the calculated value in Equation 4 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
SMART
REGULATOR
Iq
Control
Features
I
Q
I
I
Figure 28. Single Output Regulator with Key
Performance Parameters Labeled
V
I
V
Q
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of R
q
JA
:
R
qJA
+ R
qJC
) R
qCS
) R
qSA
(eq. 5)
where:
R
q
JC
is the junction-to-case thermal resistance,
R
q
CS
is the case-to-heatsink thermal resistance,
R
q
SA
is the heatsink-to-ambient thermal resistance.
R
q
JC
appears in the package section of the data sheet.
Like R
q
JA
, it too is a function of package type. R
q
CS
and
R
q
SA
are functions of the package type, heatsink and the
interface between them. These values appear in data sheets
of heatsink manufacturers.
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
Thermal Model
See pages 13 to 16 for detailed information about thermal
model parameters.

NCV4276BDT50RKG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators 5V 400 MA LDO REG
Lifecycle:
New from this manufacturer.
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