MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
_______________________________________________________________________________________ 7
Note 16: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
bit = 0. PSR at 60Hz exceeds 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
Note 17: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
Note 18: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
When used with a resonator or crystal between CLKIN and CLKOUT, the actual power dissipation and I
DD
in standby
mode depends on the resonator or crystal type.
TIMING CHARACTERISTICS
(V+ = +5V ±5%, V
DD
= +2.7V to +5.25V, AGND = DGND, f
CLKIN
= 2.4576MHz; input logic 0 = 0V; logic 1 = V
DD
, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.) (Notes 19, 20, 21)
0100V
DD
= 3.3V
V
DD
= 5V
V
DD
= 3.3V
V
DD
= 5V
Bus Relinquish Time After SCLK
Rising Edge (Note 26)
t
10
10 100
ns
SCLK Falling Edge to Data Valid
Delay (Notes 24, 25)
t
6
080
ns
INT High Time
t
INT
560 / N
x t
CLKIN
ns
X2CLK = 1, N = 2
(2 x MF1 + MF0)
X2CLK = 1
X2CLK = 0
SCLK Setup to Falling Edge CS
t
4
30 ns
SCLK Low Pulse Width t
8
100 ns
10 70
100 nsV
DD
= 5V
CS Rising Edge to SCLK Rising
Edge Hold Time
t
9
0 ns(Note 21)
SCLK High Pulse Width t
7
100 ns
CS Falling Edge to SCLK Falling
Edge Setup Time
t
5
30 ns
280 / N
xt
CLKIN
INT to CS Setup Time
t
3
X2CLK = 0, N = 2
(2 x MF1 + MF0)
0 ns(Note 8)
RESET Pulse Width Low
t
2
100 ns
Master Clock Input Low Time f
CLKIN LO
0.4 x
t
CLKIN
nst
CLKIN
= 1 / f
CLKIN
, X2CLK = 0
Master Clock Input High Time f
CLKIN HI
0.4 x
t
CLKIN
nst
CLKIN
= 1 / f
CLKIN
, X2CLK = 0
Master Clock Frequency f
CLKIN
0.8 5.0
MHz
Crystal oscillator or clock
externally supplied for
specified performance
(Notes 22, 23)
PARAMETER SYMBOL MIN TYP MAX UNITS
0.4 2.5
CONDITIONS
SCLK Rising Edge to INT High
(Note 27)
t
11
200 nsV
DD
= 3.3V
SERIAL-INTERFACE READ OPERATION
MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
8 _______________________________________________________________________________________
TIMING CHARACTERISTICS (continued)
(V+ = +5V ±5%, V
DD
= +2.7V to +5.25V, AGND = DGND, f
CLKIN
= 2.4576MHz; input logic 0 = 0V; logic 1 = V
DD
, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.) (Notes 19, 20, 21)
Note 19: All input signals are specified with t
r
= t
f
= 5ns (10% to 90% of V
DD
).
Note 20: See Figure 4.
Note 21: Timings shown in tables are for the case where SCLK idles high between accesses. The part may also be used with the
SCLK idling low between accesses, provided CS is toggled. In this case SCLK in the timing diagrams should be inverted
and the terms “SCLK Falling Edge” and “SCLK Rising Edge” exchanged in the specification tables. If CS is permanently
tied low, the part should only be operated with SCLK idling high between accesses.
Note 22: CLKIN duty cycle range is 45% to 55%. CLKIN must be supplied whenever the MAX1400 is not in standby mode. If no
clock is present, the device can draw higher current than specified.
Note 23: The MAX1400 is production tested with f
CLKIN
at 2.5MHz (1MHz for some I
DD
tests).
Note 24: Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
Note 25: For read operations, SCLK active edge is falling edge of SCLK.
Note 26: Derived from the time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The number is then
extrapolated back to remove effects of charging or discharging the 50pF capacitor. This ensures that the times quoted in
the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances.
Note 27: INT returns high after the first read after an output update. The same data can be read again while INT is high, but be
careful not to allow subsequent reads to occur close to the next output update.
CS Rising Edge to SCLK Rising
Edge Hold Time
t
18
0 ns
SCLK High Pulse Width t
16
100 ns
SCLK Low Pulse Width t
17
100 ns
Data Valid to SCLK Rising Edge
Hold Time
t
15
0 ns
PARAMETER SYMBOL MIN TYP MAX UNITS
CS Falling Edge to SCLK Falling
Edge Setup Time
t
13
30 ns
Data Valid to SCLK Rising Edge
Setup Time
t
14
30 ns
SCLK Setup to Falling Edge CS
t
12
30 ns
CONDITIONS
SERIAL-INTERFACE WRITE OPERATION
800µA
at V
DD
= +5V
100µA
at V
DD
= +3.3V
100µA
at V
DD
= +3.3V
TO
OUTPUT
PIN
50pF
200µA
at V
DD
= +5V
Figure 1. Load Circuit for Bus Relinquish Time and V
OL
and
V
OH
Levels
MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
_______________________________________________________________________________________ 9
Pin Description
15 AIN5
Analog Input Channel 5. Used as a differential or pseudo-differential input with AIN6 (see the
Communications Register section).
NAME FUNCTION
1 CLKIN
Clock Input. A crystal can be connected across CLKIN and CLKOUT. Alternatively, drive CLKIN with a
CMOS-compatible clock at a nominal frequency of 2.4576MHz or 1.024MHz, and leave CLKOUT uncon-
nected. Frequencies of 4.9152MHz and 2.048MHz can be used if the X2CLK control bit is set to 1.
PIN
2 CLKOUT
Clock Output. When deriving the master clock from a crystal, connect the crystal between CLKIN and
CLKOUT. In this mode, the on-chip clock signal is not available at CLKOUT. Leave CLKOUT unconnected
when CLKIN is driven with an external clock.
3
CS
Chip-Select Input. Active-low logic input used to enable the digital interface. With CS hard-wired low, the
MAX1400 operates in its 3-wire interface mode with SCLK, DIN and DOUT used to interface to the device.
CS is used either to select the device in systems with more than one device on the serial bus, or as a
frame-synchronization signal for the MAX1400 when a continuous SCLK is used.
4
RESET
Active Low Reset Input. Drive low to reset the control logic, interface logic, digital filter and analog modu-
lator to power-on status. RESET must be high and CLKIN must be toggling in order to exit reset.
5 MUXOUT+
Positive Analog Mux Output. The positive differential output signal from the part’s internal input multiplex-
er. Use this signal in conjunction with MUXOUT- and a high-quality external amplifier for additional signal
processing before conversion. Return the processed output through ADCIN+ and ADCIN-. Connect
MUXOUT+ directly to ADCIN+ if external processing is not required.
6 MUXOUT-
Negative Analog Mux Output. The negative differential output signal from the part’s internal input multi-
plexer. Use this signal in conjunction with MUXOUT+ and a high-quality external amplifier for additional
signal processing before conversion. Return the processed output through ADCIN+ and ADCIN-.
Connect MUXOUT- directly to ADCIN- if external processing is not required.
7 ADCIN+
Positive Analog Input. A direct input to the positive buffer and the positive differential input terminal of the
ADC, bypassing the input mux. This signal forms a differential input pair with ADCIN-. Connect ADCIN+ to
MUXOUT+ when direct access is not required.
8 ADCIN-
Negative Analog Input. A direct input to the negative buffer and the negative differential input terminal of
the ADC - bypassing the input mux. This signal forms a differential input pair with ADCIN+. Connect
ADCIN- to MUXOUT- when direct access is not required.
9 AGND Analog Ground. Reference point for the analog circuitry. AGND connects to the IC substrate.
10 V+ Analog Positive Supply Voltage (+4.75V to +5.25V)
11 AIN1
Analog Input Channel 1. Can be used as a pseudo-differential input with AIN6 as common, or as the posi-
tive input of the AIN1/AIN2 differential analog input pair (see the Communications Register section).
12 AIN2
Analog Input Channel 2. Can be used as a pseudo-differential input with AIN6 as common, or as the neg-
ative input of the AIN1/AIN2 differential analog input pair (see the Communications Register section).
13 AIN3
Analog Input Channel 3. Can be used as a pseudo-differential input with AIN6 as common, or as the posi-
tive input of the AIN3/AIN4 differential analog input pair (see the Communications Register section).
14 AIN4
Analog Input Channel 4. Can be used as a pseudo-differential input with AIN6 as common, or as the neg-
ative input of the AIN3/AIN4 differential analog input pair (see the Communications Register section).
16 AIN6
Analog Input 6. Can be used as a common point for AIN1 through AIN5 in pseudo-differential mode, or as
the negative input of the AIN5/AIN6 differential analog input pair (see the Communications Register section).

MAX1400EAI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 18-Bit 5Ch 4.8ksps 2.5V Precision ADC
Lifecycle:
New from this manufacturer.
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