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5V49EE701-075NDGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
IDT5V49EE701
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 25
IDT5V49EE701 REV P 071015
Programming Registers Table
Addr
Default
Register
Hex
Value
Bit #
Description
7654321 0
0x00 00
Reserved HW/SW
Hardware/Software Mode control
HW/SW - 0=HW, 1=SW
0x01 00
Reserved SEL[2:0]
SEL[2:0] - selects configuration in
SW mode
0x02 02
SP OE6 OE5 OE4 OE3 OE2 OE1 OE0
OEx=Output Power Suspend
function for OUTx (‘1’=OUTx will
be suspended on SD/OE pin.
Disable mode is defined by OEMx
bits), ‘0’=outputs enabled and no
association with OE pin (default).
0x03 02
Reserved
OS*[6:0] OS*[6:0] - output suspend, active
low. Overwrites OE setting.
0x04 0F
SH Reserved PLLS*[3:0]
PLLS*[3:0] - PLL Suspend, active
low
SH - shutdown/OE configuration
0x05 04
Reserved XTCLKSEL Reserved
XTCLKSEL - crystal/clock select.
0=Crytal, 1=ICLK
0x06 00
Reserved
0x07 00
Reserved
XTAL[4:0] XTAL[4:0] - crystal cap
0x08 00
Reserved
0x09 00
Reserved
0x0A 10
CZ0_CFG4 IP0[2:0]_CFG4 RZ0[3:0]_CFG4
PLL0 loop parameter
0x0B 10
CZ0_CFG5 IP0[2:0]_CFG5 RZ0[3:0]_CFG5
0x0C 10
CZ0_CFG0 IP0[2:0]_CFG0 RZ0[3:0]_CFG0
0x0D 10
CZ0_CFG1 IP0[2:0]_CFG1 RZ0[3:0]_CFG1
0x0E 10
CZ0_CFG2 IP0[2:0]_CFG2 RZ0[3:0]_CFG2
0x0F 10
CZ0_CFG3 IP0[2:0]_CFG3 RZ0[3:0]_CFG3
0x10 00
Reserved D0[6:0]_CFG0
PLL0 input divider and input sel
D0[6:0] - 127 step Ref Div
D0 = 0 means power down.
0x11 00
Reserved D0[6:0]_CFG1
0x12 00
Reserved D0[6:0]_CFG2
0x13 00
Reserved D0[6:0]_CFG3
0x14 00
Reserved D0[6:0]_CFG4
0x15 00
Reserved D0[6:0]_CFG5
0x16 01
N0[7:0]_CFG4
N - Feedback Divider
2 - 4095 (values of “0” and “1” are
not allowed) Total feedback with
A, using provided calculation
0x17 01
N0[7:0]_CFG5
0x18 01
N0[7:0]_CFG0
0x19 01
N0[7:0]_CFG1
0x1A 01
N0[7:0]_CFG2
0x1B 01
N0[7:0]_CFG3
0x1C 00
A0[3:0]_CFG0 N0[11:8]_CFG0
0x1D 00
A0[3:0]_CFG1 N0[11:8]_CFG1
0x1E 00
A0[3:0]_CFG2 N0[11:8]_CFG2
0x1F 00
A0[3:0]_CFG3 N0[11:8]_CFG3
0x20 00
A0[3:0]_CFG4 N0[11:8]_CFG4
0x21 00
A0[3:0]_CFG5 N0[11:8]_CFG5
0x22 10
CZ1_CFG4 IP1[2:0]_CFG4 RZ1[3:0]_CFG4
PLL1 Loop Parameter
0x23 10
CZ1_CFG5 IP1[2:0]_CFG5 RZ1[3:0]_CFG5
0x24 10
CZ1_CFG0 IP1[2:0]_CFG0 RZ1[3:0]_CFG0
0x25 10
CZ1_CFG1 IP1[2:0]_CFG1 RZ1[3:0]_CFG1
0x26 10
CZ1_CFG2 IP1[2:0]_CFG2 RZ1[3:0]_CFG2
0x27 10
CZ1_CFG3 IP1[2:0]_CFG3 RZ1[3:0]_CFG3
IDT5V49EE701
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 26
IDT5V49EE701 REV P 071015
0x28 00
Reserved D1[6:0]_CFG0
PLL1 input divider and input sel
D1[6:0] - 127 step Ref Div
D1 = 0 means power down.
0x29 00
Reserved D1[6:0]_CFG1
0x2A 00
Reserved D1[6:0]_CFG2
0x2B 00
Reserved D1[6:0]_CFG3
0x2C 00
Reserved D1[6:0]_CFG4
0x2D 00
Reserved D1[6:0]_CFG5
0x2E 01
N1[7:0]_CFG4
N - Feedback Divider
2 - 4095 (value of “0” is not
allowed) Total feedback with A,
using provided calculation
0x2F 01
N1[7:0]_CFG5
0x30 01
N1[7:0]_CFG0
0x31 01
N1[7:0]_CFG1
0x32 01
N1[7:0]_CFG2
0x33 01
N1[7:0]_CFG3
0x34 00
N3[11:8]_CFG0 N1[11:8]_CFG0
PLL3 Feedback Divider
0x35 00
N3[11:8]_CFG1 N1[11:8]_CFG1
0x36 00
N3[11:8]_CFG2 N1[11:8]_CFG2
0x37 00
N3[11:8]_CFG3 N1[11:8]_CFG3
0x38 00
N3[11:8]_CFG4 N1[11:8]_CFG4
0x39 00
N3[11:8]_CFG5 N1[11:8]_CFG5
0x3A 00
CZ2_CFG4 IP2[2:0]_CFG4 RZ2[3:0]_CFG4
PLL2 Loop Parameter
0x3B 00
CZ2_CFG5 IP2[2:0]_CFG5 RZ2[3:0]_CFG5
0x3C 00
CZ2_CFG0 IP2[2:0]_CFG0 RZ2[3:0]_CFG0
0x3D 00
CZ2_CFG1 IP2[2:0]_CFG1 RZ2[3:0]_CFG1
0x3E 00
CZ2_CFG2 IP2[2:0]_CFG2 RZ2[3:0]_CFG2
0x3F 00
CZ2_CFG3 IP2[2:0]_CFG3 RZ2[3:0]_CFG3
0x40 00
Reserved D2[6:0]_CFG0
PLL2 Reference Divide and Input
Select
D2[6:0] - 127 step Ref Div
D2 = 0 means power down.
0x41 00
Reserved D2[6:0]_CFG1
0x42 00
Reserved D2[6:0]_CFG2
0x43 00
Reserved D2[6:0]_CFG3
0x44 00
Reserved D2[6:0]_CFG4
0x45 00
Reserved D2[6:0]_CFG5
0x46 01
N2[7:0]_CFG4
N2[7:0] - PLL2 Feedback Divider
2 - 4095 (value of “0” is not
allowed).
(See Addr 0x4C:0x51 for
N2[15:8])
0x47 01
N2[7:0]_CFG5
0x48 01
N2[7:0]_CFG0
0x49 01
N2[7:0]_CFG1
0x4A 01
N2[7:0]_CFG2
0x4B 01
N2[7:0]_CFG3
0x4C 80
SSENB_CFG0 0 0
IP3[4]_CFG0
N2[11:8]_CFG0
N2[11:8] - PLL2 Feedback Divide
PLL3 Spread Spectrum
SSENB - Spread Spectrum
Enable
SSENB = 1 means ON
IP3[4:0] - PLL3 Charge Pump
Current.
0x4D 80
SSENB_CFG1 0 0
IP3[4]_CFG1
N2[11:8]_CFG1
0x4E 80
SSENB_CFG2 0 0
IP3[4]_CFG2
N2[11:8]_CFG2
0x4F 80
SSENB_CFG3 0 0
IP3[4]_CFG3
N2[11:8]_CFG3
0x50 80
SSENB_CFG4 0 0
IP3[4]_CFG4
N2[11:8]_CFG4
0x51 80
SSENB_CFG5 0 0
IP3[4]_CFG5
N2[11:8]_CFG5
0x52 XX
1
Reserved
0x53 XX
1
Reserved
0x54 XX
1
Reserved
0x55 XX
1
Reserved
Addr
Default
Register
Hex
Value
Bit #
Description
7654321 0
IDT5V49EE701
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 27
IDT5V49EE701 REV P 071015
0x56 00
IP3[3:0]_CFG4 RZ3[3:0]_CFG4
PLL3 Loop Parameter
0x57 00
IP3[3:0]_CFG5 RZ3[3:0]_CFG5
0x58 00
IP3[3:0]_CFG0 RZ3[3:0]_CFG0
0x59 00
IP3[3:0]_CFG1 RZ3[3:0]_CFG1
0x5A 00
IP3[3:0]_CFG2 RZ3[3:0]_CFG2
0x5B 00
IP3[3:0]_CFG3 RZ3[3:0]_CFG3
0x5C 03
Reserved D3[6:0]_CFG0
PLL3 Reference Divide and input
sel
D3[6:0] - 127 step Ref Div
D3 = 0 means power down.
0x5D 03
Reserved D3[6:0]_CFG1
0x5E 03
Reserved D3[6:0]_CFG2
0x5F 03
Reserved D3[6:0]_CFG3
0x60 03
Reserved D3[6:0]_CFG4
0x61 03
Reserved D3[6:0]_CFG5
0x62 0C
N3[7:0]_CFG4
N - Feedback Divider
12 - 4095 (values of “0” through
“11” are not allowed)
0x63 0C
N3[7:0]_CFG5
0x64 0C
N3[7:0]_CFG0
0x65 0C
N3[7:0]_CFG1
0x66 0C
N3[7:0]_CFG2
0x67 0C
N3[7:0]_CFG3
0x68 00
SSVCO[7:0]_CFG0
SSVCO[7:0] - PLL3 Spread
Spectrum Loop Feedback
Counter
See Addr 0x80:0x85 for
SSVCO[15:8]
0x69 00
SSVCO[7:0]_CFG1
0x6A 00
SSVCO[7:0]_CFG2
0x6B 00
SSVCO[7:0]_CFG3
0x6C 00
SSVCO[7:0]_CFG4
0x6D 00
SSVCO[7:0]_CFG5
0x6E 00
SS_D3[7:0]_CFG4
SS_D[7:0] - PLL3 Spread
Spectrum Reference Divide
0x6F 00
SS_D3[7:0]_CFG5
0x70 00
SS_D3[7:0]_CFG0
0x71 00
SS_D3[7:0]_CFG1
0x72 00
SS_D3[7:0]_CFG2
0x73 00
SS_D3[7:0]_CFG3
0x74 01
Reserved
Reserved
0x75 03
OEM0[1:0] SLEW0[1:0] INV0 Reserved S1 S3
Output Controls
S1=1 - OUT1/OUT2 are from
DIV1/DIV2 respectively
S1=0 - Both from DIV2
S3 =1 - OUT3/OUT6 are from
DIV3/DIV6
S3=0 - Both from DIV6
SLEW# - LVTTL only
OEM#–output enable mode
x0 - tristated
01 - park low
11 - park high
OEM0 controls OUT0 only
0x76 00
OEM1[1:0] SLEW1[1:0] INV1[1:0] LVL1[1:0]
Output Controls
LVL1[1:0] - output pair
OUT1/OUT2
[00] - LVTTL
[01] - LVDS
[10] - LVPECL
[11] - HCSL
INV1 [CLK1, CLK2]
[0] - normal
[1] - invert clock
OEM1 controls OUT1/OUT2
Addr
Default
Register
Hex
Value
Bit #
Description
7654321 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

5V49EE701-075NDGI8

Mfr. #:
Buy 5V49EE701-075NDGI8
Manufacturer:
IDT
Description:
Clock Generators & Support Products VERSACLOCK PROGRAMMABLE PLL
Lifecycle:
New from this manufacturer.
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