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ATF1502AS(L)
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Figure 1. ATF1502AS Macrocell
Product Terms and
Select Mux
Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs
all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to
the macrocell logic gates and control signals. The PTMUX programming is determined by the
design compiler, which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic
The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a
single macrocell, all the product terms can be routed to the OR gate, creating a 5-input
AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be
expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-
tions. One input to the XOR comes from the OR sum term. The other XOR input can be a
product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows
polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of
product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.
Flip-flop The ATF1502AS’s flip-flop has very flexible data and control functions. The data input can
come from either the XOR gate, from a separate product term or directly from the I/O pin.
Selecting the separate product term allows creation of a buried registered feedback within a
combinatorial output macrocell. (This feature is automatically implemented by the fitter soft-
ware). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-
through latch. In this mode, data passes through when the clock is high and is latched when
the clock is low.
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ATF1502AS(L)
0995J–PLD–09/02
The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual prod-
uct term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used
as the clock, one of the macrocell product terms can be selected as a clock enable. When the
clock enable function is active and the enable signal (product term) is low, all clock edges are
ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear
(GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a prod-
uct term. The asynchronous preset (AP) can be a product term or always off.
Extra Feedback The ATF1502AS(L) macrocell output can be selected as registered or combinatorial. The
extra buried feedback signal can be either combinatorial or a registered signal regardless of
whether the output is combinatorial or registered. (This enhancement function is automatically
implemented by the fitter software.) Feedback of a buried combinatorial output allows the cre-
ation of a second latch within a macrocell.
I/O Control The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-
vidually configured as an input, output or for bi-directional operation. The output enable for
each macrocell can be selected from the true or compliment of the two output enable pins, a
subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done
by the fitter software when the I/O is configured as an input, all macrocell resources are still
available, including the buried feedback, expander and cascade logic.
Global Bus/Switch
Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from
the global bus. Under software control, up to 40 of these signals can be selected as inputs to
the logic block.
Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus
and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s
product terms. The four foldback terms in each region allow generation of high fan-in sum
terms (up to nine product terms) with little additional delay.
Programmable
Pin-keeper
Option for
Inputs and I/Os
The ATF1502AS offers the option of programming all input and I/O pins so that pin-keeper cir-
cuits can be utilized. When any pin is driven high or low and then subsequently left floating, it
will stay at that previous high or low level. This circuitry prevents unused input and I/O lines
from floating to intermediate voltage levels, which causes unnecessary power consumption
and system noise. The keeper circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
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ATF1502AS(L)
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Input Diagram
I/O Diagram
Speed/Power
Management
The ATF1502AS has several built-in speed and power management features. The
ATF1502AS contains circuitry that automatically puts the device into a low-power standby
mode when no logic transitions are occurring. This not only reduces power consumption dur-
ing inactive periods, but also provides proportional power savings for most applications
running at system speeds below 50 MHz. This feature may be selected as a design option.
To further reduce power, each ATF1502AS macrocell has a reduced-power bit feature. This
feature allows individual macrocells to be configured for maximum power savings. This feature
may be selected as a design option.
The ATF1502AS also has an optional power-down mode. In this mode, current drops to below
10 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be
used to power down the part. The power-down option is selected in the design source file.
When enabled, the device goes into power-down when either PD1 or PD2 is high. In the
power-down mode, all internal logic signals are latched and held, as are any enabled outputs.

ATF1502ASL-25AC44

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
CPLD - Complex Programmable Logic Devices CPLD 32 MACROCELL ISP LO-PWR 5V-25NS
Lifecycle:
New from this manufacturer.
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