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PCA9548ABS,118

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PCA9548A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 1 October 2015 7 of 30
NXP Semiconductors
PCA9548A
8-channel I
2
C-bus switch with reset
6.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9548A has been addressed. The
contents of the control byte are used to determine which channel is to be selected. When
a channel is selected, the channel will become active after a STOP condition has been
placed on the I
2
C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when
the channel is made active, so that no false conditions are generated at the time of
connection.
Remark: Multiple channels can be enabled at the same time. Example: B7 = 0, B6 = 1,
B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0, means that channels 7, 5, 4, 1 and 0 are
disabled and channels 6, 3, and 2 are enabled. Care should be taken not to exceed the
maximum bus capacitance. Default condition is all zeroes.
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of t
w(rst)L
, the PCA9548A will reset
its register and I
2
C-bus state machine and will deselect all channels. The RESET input
must be connected to V
DD
through a pull-up resistor.
6.4 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9548A in
a reset condition until V
DD
has reached V
POR
. At this point, the reset condition is released
and the PCA9548A register and I
2
C-bus state machine are initialized to their default
states (all zeroes) causing all the channels to be deselected. Thereafter, V
DD
must be
lowered below 0.2 V for at least 5 s in order to reset the device.
Table 4. Control register: Write—channel selection; Read—channel status
B7 B6 B5 B4 B3 B2 B1 B0 Command
XXXXXXX
0 channel 0 disabled
1 channel 0 enabled
XXXXXX
0
X
channel 1 disabled
1 channel 1 enabled
XXXXX
0
XX
channel 2 disabled
1 channel 2 enabled
XXXX
0
XXX
channel 3 disabled
1 channel 3 enabled
XXX
0
XXXX
channel 4 disabled
1 channel 4 enabled
XX
0
XXXXX
channel 5 disabled
1 channel 5 enabled
X
0
XXXXXX
channel 6 disabled
1 channel 6 enabled
0
XXXXXXX
channel 7 disabled
1 channel 7 enabled
PCA9548A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 1 October 2015 8 of 30
NXP Semiconductors
PCA9548A
8-channel I
2
C-bus switch with reset
6.5 Voltage translation
The pass gate transistors of the PCA9548A are constructed such that the V
DD
voltage can
be used to limit the maximum voltage that will be passed from one I
2
C-bus to another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the
PCA9548A is only tested at the points specified in Section 11 “
Static characteristics” of
this data sheet). In order for the PCA9548A to act as a voltage translator, the V
o(sw)
voltage should be equal to, or lower than the lowest bus voltage. For example, if the main
bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then V
o(sw)
should be equal to or below 2.7 V to effectively clamp the downstream bus voltages.
Looking at Figure 7
, we see that V
o(sw)(max)
will be at 2.7 V when the PCA9548A supply
voltage is 3.5 V or lower, so the PCA9548A supply voltage could be set to 3.3 V. Pull-up
resistors can then be used to bring the bus voltages to their appropriate levels (see
Figure 14
).
More Information can be found in Application Note AN262: PCA954X family of I
2
C/SMBus
multiplexers and switches.
(1) maximum
(2) typical
(3) minimum
Fig 7. Pass gate voltage versus supply voltage
PCA9548A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
Product data sheet Rev. 5.1 — 1 October 2015 9 of 30
NXP Semiconductors
PCA9548A
8-channel I
2
C-bus switch with reset
7. Characteristics of the I
2
C-bus
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8
).
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 9
).
7.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10
).
Fig 8. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 9. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
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PCA9548ABS,118

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Buy PCA9548ABS,118
Manufacturer:
NXP Semiconductors
Description:
Multiplexer Switch ICs 8CH I2C SWTCH W/REST
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