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XRT75L02DIV-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
XRT75L02
xr
xrxr
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
REV. 1.0.3
23
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( T
A
= 25
0
C, V
DD
=3.3V± 5%
AND
LOAD
= 10
P
F)
S
YMBOL
P
ARAMETER
M
IN
. T
YP
. M
AX
U
NITS
t
21
CS Low to Rising Edge of SClk 5 ns
t
22
SDI to Rising Edge of SClk 5 ns
t
23
SDI to Rising Edge of SClk Hold Time 5 ns
t
24
SClk "Low" Time 25 ns
t
25
SClk "High" Time 25 ns
t
26
SClk Period 50 ns
t
27
Falling Edge of SClk to rising edge of CS 0 ns
t
28
CS "Inactive" Time 50 ns
t
29
Falling Edge of SClk to SDO Valid Time 20 ns
t
30
Falling Edge of SClk to SDO Invalid Time 10 ns
t
31
Rising edge of CS to High Z 10 ns
t
32
Rise/Fall time of SDO Output 5 ns
xr
xrxr
xr
XRT75L02
REV. 1.0.3
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
24
4.0 THE TRANSMITTER SECTION:
The Transmitter Section, within each Channel, accepts TTL/CMOS level signals from the Terminal Equipment
in selectable data formats.
•
Convert the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the
various industry standard pulse template requirements. Figures 7, 8 and 9 illustrate the pulse template
requirements.
•
Encode the un-encoded NRZ data into either B3ZS format (for DS3 or STS-1) or HDB3 format (for E3) and
convert to pulses with shapes and width that are compliant with industry standard pulse template
requirements. Figures 7, 8 and 9 illustrate the pulse template requirements.
•
In Single-Rail or un-encoded Non-Return-to-Zero (NRZ) mode, data is input via TPOS_n pins while TNEG_n
pins must be grounded. The NRZ or Single-Rail mode is selected when the SR/DR input pin is “High” (in
Hardware Mode) or bit 0 of channel control register is “1” (in Host Mode). Figure 12 illustrates the Single-Rail
or NRZ format.
•
In Dual-Rail mode, data is input via TPOS_n and TNEG_n pins. TPOS_n contains positive data and
TNEG_n contains negative data. The SR/DR input pin = “Low” (in Hardware Mode) or bit 0 of channel
register = “0” (in Host Mode) enables the Dual-Rail mode. Figure 13 illustrates the Dual-Rail data format.
4.1 T
RANSMIT
C
LOCK
:
The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736
MHz or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle
clock to the pulse shaping circuit. This allows a 30% to 70% duty cycle Transmit Clock to be supplied.
4.2 B3ZS/HDB3 E
NCODER
:
When the Single-Rail (NRZ) data format is selected, the Encoder Block encodes the data into either B3ZS
format (for either DS3 or STS-1) or HDB3 format (for E3).
4.2.1 B3ZS Encoding:
An example of B3ZS encoding is shown in Figure 14. If the encoder detects an occurrence of three
consecutive zeros in the data stream, it is replaced with either B0V or 00V, where ‘B’ refers to Bipolar pulse
F
IGURE
12. S
INGLE
-R
AIL
OR
NRZ D
ATA
F
ORMAT
(E
NCODER
AND
D
ECODER
ARE
E
NABLED
)
F
IGURE
13. D
UAL
-R
AIL
D
ATA
F
ORMAT
(
ENCODER
AND
DECODER
ARE
DISABLED
)
TxClk
TPData
Data 1 1 0
0
TxClk
TPData
TNData
Data 1 1 0
0
XRT75L02
xr
xrxr
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
REV. 1.0.3
25
that is compliant with the Alternating polarity requirement of the AMI (Alternate Mark Inversion) line code and
‘V’ refers to a Bipolar Violation (e.g., a bipolar pulse that violates the AMI line code). The substitution of B0V or
00V is made so that an odd number of bipolar pulses exist between any two consecutive violation (V) pulses.
This avoids the introduction of a DC component into the line signal.
4.2.2 HDB3 Encoding:
An example of the HDB3 encoding is shown in Figure 15. If the HDB3 encoder detects an occurrence of four
consecutive zeros in the data stream, then the four zeros are substituted with either 000V or B00V pattern. The
substitution code is made in such a way that an odd number of bipolar (B) pulses exist between any
consecutive V pulses. This avoids the introduction of DC component into the analog signal.
N
OTES
:
1. When Dual-Rail data format is selected, the B3ZS/HDB3 Encoder is automatically disabled.
2. In Dual-Rail format, the Bipolar Violations in the incoming data stream is converted to valid data pulses.
3. Encoder and Decoder is enabled only in Single-Rail mode.
4.3 T
RANSMIT
P
ULSE
S
HAPER
:
The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark
Inversion (AMI) pulse that meet the industry standard mask template requirements for STS-1 and DS3. See
Figures 8 and 9.
For E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped
pulse with very little slope. This is illustrated in Figure 7.
The Pulse Shaper Block also includes a Transmit Build Out Circuit, which can either be disabled or enabled by
setting the TxLEV_n input pin “High” or “Low” (in Hardware Mode) or setting the TxLEV_n bit to “1” or “0” in the
control register (in Host Mode).
For DS3/STS-1 rates, the Transmit Build Out Circuit is used to shape the transmit waveform that ensures that
transmit pulse template requirements are met at the Cross-Connect system. The distance between the
transmitter output and the Cross-Connect system can be between 0 to 450 feet.
F
IGURE
14. B3ZS E
NCODING
F
ORMAT
F
IGURE
15. HDB3 E
NCODING
F
ORMAT
0 0 01
1
1
1
111
VB
V
1
00 00 0 0
0000
0
0
00 0 0V
B V
00 0
TClk
Line
Signal
TPDATA
00
0 0 01
1
1
1
111
VB
V
1
00 00 0 0
0000
0
0
0
0 0
V
00 0
TClk
Line
Signal
TPDATA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

XRT75L02DIV-F

Mfr. #:
Buy XRT75L02DIV-F
Manufacturer:
MaxLinear
Description:
Telecom Interface ICs 2-Ch E3/DS3/STS-1
Lifecycle:
New from this manufacturer.
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