XRT75L02
xr
xrxr
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
REV. 1.0.3
29
T
RAINING
M
ODE
:
In the absence of input signals at RTIP_n and RRING_n pins, or when the frequency difference between the
recovered line clock signal and the reference clock applied on the E3/DS3/STS1CLK input pins exceed 0.5%,
a Loss of Lock condition is declared by toggling RLOL_n output pin “High” (in Hardware Mode) or setting the
RLOL_n bit to “1” in the control registers. Also, the clock output on the RxClk_n pins are the same as the
reference clock applied on E3/DS3/STS1CLK pins.
D
ATA
/C
LOCK
R
ECOVERY
M
ODE
:
In the presence of input line signals on the RTIP_n and RRING_n input pins and when the frequency
difference between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that
is output on the RxClk_n out pins is the Recovered Clock signal.
5.3 B3ZS/HDB3 Decoder:
The decoder block takes the output from clock and data recovery block and decodes the B3ZS (for DS3 or
STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data
stream.
When the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three (for
B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV_n
output pins to indicate line code violation.
N
OTE
: In Single- Rail (NRZ) mode, the decoder is bypassed.
5.4 LOS (Loss of Signal) Detector:
5.4.1 DS3/STS-1 LOS Condition:
A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line.
When the DLOS condition occurs, the DLOS_n bit is set to “1” in the status control register. DLOS condition is
cleared when the detected average pulse density is greater than 33% for 175 ± 75 pulses.
Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the
threshold as shown in the Table 10.The status of the ALOS condition is reflected in the ALOS_n status control
register.
RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output
pin is toggled “High” and the RLOS_n bit is set to “1” in the status control register.
D
ISABLING
ALOS/DLOS D
ETECTION
:
For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Setting both ALOSDIS_n and
DLOSDIS_n bits disables the LOS detection on a per channel basis.
5.4.2 E3 LOS Condition:
If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the
LOS condition is detected. Loss of signal level is defined to be between 15 and 35 dB below the normal level.
If the signal drops below 35 dB for 175 ± 75 consecutive pulse periods, LOS condition is declared. This is
illustrated in Figure 19.
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
REQEN (DS3
AND
STS-1 A
PPLICATIONS
)
A
PPLICATION
REQEN S
ETTING
S
IGNAL
L
EVEL
TO
D
ECLARE
ALOS S
IGNAL
L
EVEL
TO
C
LEAR
ALOS
DS3
0 <17 mV >70 mV
1 <20 mV >90 mV
STS-1
0 <20 mV >90 mV
1 <25 mV >115 mV
