AD8510/AD8512/AD8513
Rev. I | Page 13 of 20
GENERAL APPLICATION INFORMATION
INPUT OVERVOLTAGE PROTECTION
The AD8510/AD8512/AD8513 have internal protective
circuitry that allows voltages as high as 0.7 V beyond the
supplies to be applied at the input of either terminal without
causing damage. For higher input voltages, a series resistor is
necessary to limit the input current. The resistor value can be
determined from the formula
mA5
S
S
IN
R
VV
With a very low offset current of <0.5 nA up to 125°C, higher
resistor values can be used in series with the inputs. A 5 kΩ
resistor protects the inputs from voltages as high as 25 V
beyond the supplies and adds less than 10 µV to the offset.
OUTPUT PHASE REVERSAL
Phase reversal is a change of polarity in the transfer function of
the amplifier. This can occur when the voltage applied at the
input of an amplifier exceeds the maximum common-mode
voltage.
Phase reversal can cause permanent damage to the device and
can result in system lockups. The AD8510/AD8512/AD8513 do
not exhibit phase reversal when input voltages are beyond the
supplies.
TIME (20µs/DIV)
02729-057
VOLTAGE (2V/DIV)
V
IN
V
OUT
V
SY
= ±5V
A
V
= 1
R
L
= 10k
Figure 41. No Phase Reversal
TOTAL HARMONIC DISTORTION (THD) + NOISE
The AD8510/AD8512/AD8513 have low THD and excellent gain
linearity, making these amplifiers great choices for precision
circuits with high closed-loop gain and for audio application
circuits. Figure 42 shows that the AD8510/AD8512/AD8513 have
approximately 0.0005% of total distortion when configured in
positive unity gain (the worst case) and driving a 100 kΩ load.
FREQUENCY (Hz)
DISTORTION (%)
02729-056
0.01
0.001
0.0001
20 100 1k 10k 20k
V
SY
= ±5V
R
L
= 100k
BW = 22kHz
Figure 42. THD + N vs. Frequency
TOTAL NOISE INCLUDING SOURCE RESISTORS
The low input current noise and input bias current of the
AD8510/AD8512/AD8513 make them the ideal amplifiers for
circuits with substantial input source resistance. Input offset
voltage increases by less than 15 nV per 500 Ω of source
resistance at room temperature. The total noise density of the
circuit is
(
)
SS
nn
nTOTAL
kTRRiee 4
2
2
++=
where:
e
n
is the input voltage noise density of the parts.
i
n
is the input current noise density of the parts.
R
S
is the source resistance at the noninverting terminal.
k is Boltzmanns constant (1.38 × 10
–23
J/K).
T is the ambient temperature in Kelvin (T = 273 + °C).
For R
S
< 3.9 kΩ, e
n
dominates and e
nTOTAL
≈ e
n
. The current noise
of the AD8510/AD8512/AD8513 is so low that its total density
does not become a significant term unless R
S
is greater than
165 MΩ, an impractical value for most applications.
The total equivalent rms noise over a specific bandwidth is
expressed as
BWee
nTOTALnTOTAL
=
where
BW is the bandwidth in hertz.
Note that the previous analysis is valid for frequencies larger
than 150 Hz and assumes flat noise above 10 kHz. For lower
frequencies, flicker noise (1/f) must be considered.
AD8510/AD8512/AD8513
Rev. I | Page 14 of 20
SETTLING TIME
Settling time is the time it takes the output of the amplifier to
reach and remain within a percentage of its final value after a
pulse is applied at the input. The AD8510/AD8512/AD8513
settle to within 0.01% in less than 900 ns with a step of 0 V to
10 V in unity gain. This makes each of these parts an excellent
choice as a buffer at the output of DACs whose settling time is
typically less than 1 µs.
In addition to the fast settling time and fast slew rate, low offset
voltage drift and input offset current maintain the full accuracy
of 12-bit converters over the entire operating temperature range.
OVERLOAD RECOVERY TIME
Overload recovery, also known as overdrive recovery, is the
time it takes the output of an amplifier to recover to its linear
region from a saturated condition. This recovery time is par-
ticularly important in applications where the amplifier must
amplify small signals in the presence of large transient voltages.
Figure 43 shows the positive overload recovery of the AD8510/
AD8512/AD8513. The output recovers in approximately 200 ns
from a saturated condition.
0V
–15V
200mV
0V
OUTPUTINPUT
VOL
T
AGE
TIME (2µs/DIV)
V
SY
= ±15V
V
IN
= 200mV
A
V
= –100
R
L
= 10k
02729-053
Figure 43. Positive Overload Recovery
The negative overdrive recovery time shown in Figure 44 is less
than 200 ns.
In addition to the fast recovery time, the AD8510/AD8512/
AD8513 show excellent symmetry of the positive and negative
recovery times. This is an important feature for transient signal
rectification because the output signal is kept equally undistorted
throughout any given period.
TIME (2µs/DIV)
VOLTAGE
–200mV
0V
0V
+15V
02729-054
INPUT OUTPUT
V
SY
= ±15V
A
V
= –100
R
L
= 10k
Figure 44. Negative Overload Recovery
CAPACITIVE LOAD DRIVE
The AD8510/AD8512/AD8513 are unconditionally stable at all
gains in inverting and noninverting configurations. Each device
is capable of driving a capacitive load of up to 1000 pF without
oscillation in unity gain using the worst-case configuration.
However, as with most amplifiers, driving larger capacitive
loads in a unity gain configuration may cause excessive
overshoot and ringing, or even oscillation. A simple snubber
network significantly reduces the amount of overshoot and
ringing. The advantage of this configuration is that the output
swing of the amplifier is not reduced, because R
S
is outside the
feedback loop.
7
4
6
AD8510
00m
R
S
C
S
C
L
V
OUT
V+
V–
02729-055
2
3
Figure 45. Snubber Network Configuration
AD8510/AD8512/AD8513
Rev. I | Page 15 of 20
Figure 46 shows a scope plot of the output of the AD8510/AD8512/
AD8513 in response to a 400 mV pulse. The circuit is configured in
positive unity gain (worst case) with a load experience of 500 pF.
TIME (1µs/DIV)
VOLTAGE (200mV/DIV)
V
SY
= ±15V
C
L
= 500pF
R
L
=10k
02729-041
Figure 46. Capacitive Load Drive Without Snubber
When the snubber circuit is used, the overshoot is reduced from
55% to less than 3% with the same load capacitance. Ringing is
virtually eliminated, as shown in Figure 47.
TIME (1µs/DIV)
VOL
T
AGE (200mV/DIV)
V
SY
= ±15V
R
L
= 10k
C
L
= 500pF
R
S
= 100
C
S
= 1nF
02729-042
Figure 47. Capacitive Load with Snubber Network
Optimum values for R
S
and C
S
depend on the load capacitance
and input stray capacitance and are determined empirically.
Tabl e 5 shows a few values that can be used as starting points.
Table 5. Optimum Values for Capacitive Loads
C
LOAD
R
S
(Ω) C
S
500 pF 100 1 nF
2 nF 70 100 pF
5 nF 60 300 pF
OPEN-LOOP GAIN AND PHASE RESPONSE
In addition to their impressive low noise, low offset voltage, and
offset current, the AD8510/AD8512/AD8513 have excellent
loop gain and phase response even when driving large resistive
and capacitive loads.
Compared with Competitor A (see Figure 49) under the same
conditions, with a 2.5 kΩ load at the output, the AD8510/AD8512/
AD8513 have more than 8 MHz of bandwidth and a phase margin
of more than 52°.
Competitor A, on the other hand, has only 4.5 MHz of band-
width and 28° of phase margin under the same test conditions.
Even with a 1 nF capacitive load in parallel with the 2 kΩ load
at the output, the AD8510/AD8512/AD8513 show much better
response than Competitor A, whose phase margin is degraded
to less than 0, indicating oscillation.
FREQUENCY (Hz)
GAIN (dB)
10k
–30
–20
–10
100k
0
10
30
1M 10M
50M
40
50
20
60
70
–135
–90
–45
0
45
90
135
180
225
270
315
PHASE (Degrees)
02729-043
V
SY
= ±15V
R
L
= 2.5k
C
L
= 0pF
Figure 48. Frequency Response of the AD8510/AD8512/AD8513
FREQUENCY (Hz)
GAIN (dB)
10k
–30
–20
–10
100k
0
10
30
1M 10M
50M
40
50
20
60
70
–135
–90
–45
0
45
90
135
180
225
270
315
PHASE (Degrees)
02729-044
V
SY
= ±15V
R
L
= 2.5k
C
L
= 0pF
Figure 49. Frequency Response of Competitor A

AD8510ARZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers Lo Noise-Inpt Bias Crnt Wide BW JFET
Lifecycle:
New from this manufacturer.
Delivery:
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