Analog Integrated Circuit Device Data
Freescale Semiconductor 7
33790
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V V
DD
5.25 V, 8.0 V V
SUP
25.0 V, -40 C T
J
150 C, unless otherwise
noted.
Characteristic Symbol Min Typ Max Unit
MICROCONTROLLER INTERFACE
Microcontroller Signal Cycle Time t
CYC
6.6 1000 s
Microcontroller Signal Low Time t
CYCL
2.0 667 s
Microcontroller Signal High Time t
CYCH
2.0 667 s
Microcontroller Signal Duty Cycle for Logic Zero DC
LO
30 33 36 %
Microcontroller Signal Duty Cycle for Logic One DC
HI
60.0 66.7 72.0 %
Microcontroller Signal Slew Time
(6)
t
SLEW
500 ns
Frame Start to Signal Delay Time t
DLY1
t
cyc
- 0.1 t
cyc
t
cyc
+ 0.1 s
Signal End to Frame End Delay Time t
DLY2
1.0 s
Rise Time
(6)
t
RISE
0 100 ns
Fall Time
(6)
t
FALL
0 100 ns
BUS TRANSMITTER
Idle to Frame and Frame to Idle Slew Rate
C 5.0 nF
t
SLEW
(FRAME)
3.0 6.0 10.0
V/s
Signal High to Low and Signal Low to High Slew Rate
C 5.0 nF
t
SLEW
(SIGNAL)
3.0 4.5 8.0
V/s
Data Valid (V
SUP
x
= 25 V, C
L
5.0 nF)
DSIxF, V
IN(TH)
to DSIxO = 5.3 V
DSIxS, V
IN(TH)
to DSIxO = 2.6 V
DSIxS, V
IN(TH)
to DSIxO = 3.4 V
DSIxF, V
IN(TH)
to DSIxO = 7.0 V
t
DVLD1
t
DVLD2
t
DVLD3
t
DVLD4
2.44
0.25
0.25
0.25
6.56
1.3
1.3
1.3
s
BUS RECEIVER
Receiver Delay Time
t
DRH
: I = I
RH
to DSIxR = 2.5 V
t
DRL
: I = I
RH
to DSIxR = 2.5 V
t
DRH
t
DRL
400
400
750
750
ns
Notes
6. Slew times and rise and fall times between 10% and 90% of output high and low levels.
Analog Integrated Circuit Device Data
8 Freescale Semiconductor
33790
ELECTRICAL CHARACTERISTICS
TIMING CHARACTERISTICS
TIMING CHARACTERISTICS
Figure 4. Timing Characteristics
Notes
7. Typical BUSIN / BUSOUT logic thresholds (V
THL
) from MC33793 datasheet.
8. t
TAT
(Turnaround Time) is dependent upon wire length, bus loads, and slave response characteristics.
9. DSIxR stable on falling edge of DSIxS or rising edge of DSIxF.
5.0 V
0 V
5.0 V
0 V
25 V
1.5 V
5.0 V
0 V
0 mA
I
RH
DSIxS
DSIxF
DSIxO
DSIxR
V
IN(TH)
V
IN(TH)
4.5 V
I
OUT
t
CYC
t
CYC
H
t
DLY2
t
CYC
L
t
RISE
t
RISE
t
FALL
t
DLY1
t
DVLD1
t
SLEW
(FRAME)
t
SLEW
(SIGNAL)
t
DVLD3
t
DVLD2
t
DRH
t
DRL
5.0 V
7.0 V
t
DVLD4
t
CYC
3.0 V
t
TAT
DSIV
OH
(Note
(9)
)
(Note
(8)
)
Note
(7)
Analog Integrated Circuit Device Data
Freescale Semiconductor 9
33790
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33790 is designed to provide the interface between logic
and the DSI bus. It accepts signals with a typical 0
V to 5.0 V
logic level to control the state of the bus output (Idle Level,
Logic High Level, Logic Low Level, and High Impedance). It
detects the current drawn from the bus output during
signaling and outputs a 0
V to 5.0 V logic level corresponding
to the bus current being above (Logic [1] out) the bus return
logic
[1] current or below (Logic [0] out). The 33790 contains
current limiting of the bus outputs as required by the DSI Bus
specification and thermal shutdown to protect itself from
damage. Two independent DSI bus outputs are provided by
the IC.
FUNCTIONAL TERMINAL DESCRIPTION
Bus Driver and Receiver
The Wave-Shaper converts the 0 to 5.0 V logic inputs from
DSIxF (frame) and DSIxS (signal) to a wave-shaped signal
on the DSIxO output, as shown in the timing diagrams in
Figure 2, page 3, and the truth table in Table 6. The Bus
Current Sense detects the current being drawn by the
device(s) on the bus during signalling (DSIxF
= 0). If the
current is above a set level, DSIxR will be high; otherwise, it
is low. Due to the variations in the turnaround time (t
TAT
) from
slave devices and bus delays, DSIxR should be sampled on
the falling edge of DSIxS and on the rising edge of DSIxF (for
the last return bit).
The current for the idle state is from the supply connected to
V
SUP
and this supply should not be current limited below
250 mA per channel. During idle state, the voltage on the DSI
bus will be very close to the V
SUP
voltage.
Internal thermal shutdown circuitry and current limit
individually protect the DSIxO outputs from shorts to battery
and ground.
Typically, the thermal shutdown occurs between 160 °C and
170 °C. If the junction temperature rises above this
temperature, the internal Tx
LIM
bit is asserted, and the output
drivers for DSIxO are disabled by the thermal shutdown
circuitry. The output drivers remain off until the junction
temperature decreases below approximately 155
°C, at
which time the thermal shutdown circuitry turns off and the
outputs are re-enabled. Each DSIxO output has a unique
thermal sense and shutdown circuit, so a short on one
channel does not affect the other channel.
Charge Pump
The charge pump uses on-board capacitors to step the input
voltage up to the voltage needed to drive the on-board
transmitter FETs. A filter
/ storage capacitor is connected to
CPCAP to hold the stepped-up voltage.
Input Pull-ups and Pull-downs
Internal current pull-ups are used on the DSIxF pins and
pulldowns on the DSIxS pins. If these pins are left
unconnected, their associated DSI bus will go to the unused
(high-impedance) state.
Table 6. DSI Bus Truth Table
DSIxF DSIxS
Tx
LIM
DSIxR DSIxO
0 0 0 Not Defined Low (1.5 V)
0 1 0 Not Defined High (4.5 V)
0 0 Return Data Unchanged
X 0 Return Data Unchanged
1 0 0 0 High Impedance
1 1 0 0 Idle V
SUP
- 0.5 V
X X 1 1 High Impedance

MC33790HEGR2

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
Interface - Specialized DISTRIB SYS INTRFC
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