SC16C751B_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 10 October 2008 22 of 32
NXP Semiconductors
SC16C751B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
[1] Except for XTAL2, V
OL
= 1 V typically.
[2] Sleep current might be higher if there is activity on the UART data bus during Sleep mode.
10. Dynamic characteristics
Table 24. Dynamic characteristics
T
amb
=
−
40
°
C to +85
°
C; tolerance of V
DD
=
±
10 %, unless otherwise specified.
Symbol Parameter Conditions V
DD
= 2.5 V V
DD
= 3.3 V V
DD
= 5.0 V Unit
Min Max Min Max Min Max
t
w2
pulse width LOW 10 -6-6-ns
t
w1
pulse width HIGH 10 -6-6-ns
f
XTAL1
frequency on pin XTAL1
[1]
-48-80-80MHz
t
6s’
address set-up time 10 - 10 - 5 - ns
t
7d
IOR delay from chip select 10 - 10 - 10 - ns
t
7w
IOR strobe width 25 pF load 77 - 26 - 23 - ns
t
7h
chip select hold time from
IOR
0-0-0-ns
t
7h’
address hold time 5-5-5-ns
t
9d
read cycle delay 25 pF load 20 - 20 - 20 - ns
t
12d
delay from IOR to data 25 pF load - 77 - 26 - 23 ns
t
12h
data disable time 25 pF load - 15 - 15 - 15 ns
t
13d
IOW delay from chip select 10 - 10 - 10 - ns
t
13w
IOW strobe width 20 - 20 - 15 - ns
t
13h
chip select hold time from
IOW
0-0-0-ns
t
14d
IOW delay from address 10 - 10 - 10 - ns
t
15d
write cycle delay 25 - 25 - 20 - ns
t
16s
data set-up time 20 - 20 - 15 - ns
t
16h
data hold time 15 -5-5-ns
t
17d
delay from IOW to output 25 pF load - 100 - 33 - 29 ns
t
18d
delay to set interrupt from
modem input
25 pF load - 100 - 24 - 23 ns
t
19d
delay to reset interrupt from
IOR
25 pF load;
Figure 7
- 100 - 24 - 23 ns
t
20d
delay from stop to set
interrupt
[2]
-1T
RCLK
-1T
RCLK
-1T
RCLK
s
t
21d
delay time IOR to reset
interrupt
25 pF load;
Figure 9
- 100 - 29 - 28 ns
t
22d
delay from start to set
interrupt
- 100 - 45 - 40 ns
t
23d
delay time from IOW to
transmit start
[2]
8T
RCLK
24T
RCLK
8T
RCLK
24T
RCLK
8T
RCLK
24T
RCLK
s
t
24d
delay from IOW to reset
interrupt
- 100 - 45 - 40 ns
t
RESET
RESET pulse width
[3]
100-40-40-ns
N baud rate divisor 1 2
16
− 112
16
− 112
16
− 1
