LTC3835
21
3835fe
For more information www.linear.com/LTC3835
APPLICATIONS INFORMATION
a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of V
OUT
for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET, and
become significant only when operating at high input
voltages (typically 15V or greater). Transition losses
can be estimated from:
Transition Loss = (1.7) V
IN
2 I
O(MAX)
C
RSS
f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C
IN
has ad-
equate charge storage and very
low ESR at the switching
frequency. A 25W supply will typically require
a minimum
of 20µF to 40µF of capacitance having a
maximum of 20mΩ
to 50mΩ of ESR. Other losses including Schottky conduc-
tion losses during dead-time and inductor core losses
generally account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by
an amount equal to ∆I
LOAD
(ESR), where ESR is the ef-
fective series resistance of C
OUT
. ∆I
LOAD
also begins to
charge or discharge C
OUT
generating the feedback error
signal that forces the regulator to adapt to the current
change and return V
OUT
to its steady-state value. During
this recovery time V
OUT
can be monitored for excessive
overshoot or ringing, which
would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values. The availability of the I
TH
pin
not only allows optimization of control loop behavior but
also provides a DC coupled and AC filtered closed loop
response test point. The DC step, rise time and settling
at this test point truly reflects the
closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
pin. The I
TH
external components shown in the Typical
Application circuit will provide an adequate starting point
for most applications.
The I
TH
series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and I
TH
pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output
voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the I
TH
pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased
by increasing R
C
and the bandwidth of the loop will be
increased by decreasing C
C
. If R
C
is increased by the same
factor that C
C
is decreased, the zero frequency will be kept
the same, thereby keeping the phase shift the same in the
