500 MHz to 1700 MHz, Dual-Balanced
Mixer, LO Buffer, IF Amplifier, and RF Balun
ADL5358
Rev. 0
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FEATURES
RF frequency range of 500 MHz to 1700 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion gain: 8.3 dB
SSB noise figure of 9.9 dB
SSB noise figure with 5 dBm blocker of 23 dB
Input IP3 of 25.2 dBm
Input P1dB of 10.6 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle, 6 mm × 6 mm, 36-lead LFCSP
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
GENERAL DESCRIPTION
The ADL5358 uses a highly linear, doubly balanced, passive
mixer core along with integrated RF and local oscillator (LO)
balancing circuitry to allow single-ended operation. The
ADL5358 incorporates the RF baluns, allowing for optimal
performance over a 500 MHz to 1700 MHz RF input frequency
range. Performance is optimized for RF frequencies from 500 MHz
to 1200 MHz using a high-side LO and RF frequencies from
1200 MHz to 1700 MHz using a low-side LO. The balanced
passive mixer arrangement provides good LO-to-RF leakage,
typically better than −20 dBm, and excellent intermodulation
performance. The balanced mixer core also provides extremely
high input linearity, allowing the device to be used in demanding
cellular applications where in-band blocking signals may otherwise
result in the degradation of dynamic performance. A high linearity
IF buffer amplifier follows the passive mixer core to yield a
typical power conversion gain of 8.3 dB and can be used with
a wide range of output impedances.
The ADL5358 provides two switched LO paths that can be used
in TDD applications where it is desirable to ping-pong between
two local oscillators. LO current can be externally set using a
resistor to minimize dc current commensurate with the desired
level of performance. For low voltage applications, the ADL5358 is
capable of operation at voltages down to 3.3 V with substantially
reduced current. Under low voltage operation, an additional logic
pin is provided to power down (<300 µA) the circuit when desired.
FUNCTIONAL BLOCK DIAGRAM
ADL5358
VGS0
VGS1
VGS2
LOSW
PWDN
VPOS
COMM
LOI2
LOI1
MNIN
MNCT
COMM
DVIN
VPOS
COMM
VPOS
COMM
DVCT
V
P
O
S
D
V
G
M
C
O
M
M
D
V
O
P
D
V
O
N
D
V
L
E
V
P
O
S
D
V
L
G
N
C
M
N
O
N
C
O
M
M
M
N
G
M
V
P
O
S
M
N
O
P
M
N
L
E
V
P
O
S
M
N
L
G
N
C
07885-001
Figure 1.
The ADL5358 is fabricated using a BiCMOS high performance
IC process. The device is available in a 6 mm × 6 mm, 36-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency
(MHz)
Single
Mixer
Single Mixer
and IF Amp
Dual Mixer
and IF Amp
500 to 1700 ADL5367 ADL5357 ADL5358
1200 to 2500 ADL5365 ADL5355 ADL5356
ADL5358
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
5 V Performance ........................................................................... 4
3.3 V Performance ........................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance ........................................................................... 7
3.3 V Performance ...................................................................... 15
Spurious Performance ............................................................... 16
Circuit Description......................................................................... 17
RF Subsystem .............................................................................. 17
LO Subsystem ............................................................................. 18
Applications Information .............................................................. 19
Basic Connections ...................................................................... 19
IF Port .......................................................................................... 19
Bias Resistor Selection ............................................................... 19
Mixer VGS Control DAC .......................................................... 19
Evaluation Board ............................................................................ 21
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
11/09—Revision 0: Initial Version
ADL5358
Rev. 0 | Page 3 of 24
SPECIFICATIONS
V
S
= 5 V, I
S
= 350 mA, T
A
= 25°C, f
RF
= 900 MHz, f
LO
= 1103 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 k, R2 = R5 = 1 k,
Z
O
= 50 Ω, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RF INPUT INTERFACE
Return Loss Tunable to >20 dB over a limited bandwidth 20 dB
Input Impedance 50 Ω
RF Frequency Range 500 1700 MHz
OUTPUT INTERFACE
Output Impedance Differential impedance, f = 200 MHz 230||0.75 Ω||pF
IF Frequency Range 30 450 MHz
DC Bias Voltage
1
Externally generated 3.3 5.0 5.5 V
LO INTERFACE
LO Power −6 0 +10 dBm
Return Loss 13 dB
Input Impedance 50 Ω
LO Frequency Range 530 1670 MHz
POWER-DOWN (PWDN) INTERFACE
2
PWDN Threshold 1.0 V
Logic 0 Level 0.4 V
Logic 1 Level 1.4 V
PWDN Response Time Device enabled, IF output to 90% of its final level 160 ns
Device disabled, supply current < 5 mA 230 ns
PWDN Input Bias Current Device enabled 0 μA
Device disabled 70 μA
1
Apply supply voltage from external circuit through choke inductors.
2
PWDN function is intended for use with V
S
≤ 3.6 V only.

ADL5358ACPZ-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RF Mixer 1,2G dual mixer, dual mixer/amp
Lifecycle:
New from this manufacturer.
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