74HC40103 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 4 — 27 January 2016 14 of 24
NXP Semiconductors
74HC40103
8-bit synchronous binary down counter
[1] t
pd
is the same as t
PHL
, t
PLH
.
[2] t
t
is the same as t
THL
, t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
t
su
set-up time PE to CP; see Figure 11
V
CC
= 2.0 V 110 - - ns
V
CC
= 4.5 V 22 - - ns
V
CC
= 6.0 V 19 - - ns
TE
to CP; see Figure 12
V
CC
= 2.0 V 225 - - ns
V
CC
= 4.5 V 45 - - ns
V
CC
= 6.0 V 38 - - ns
Pn to CP; see Figure 11
V
CC
= 2.0 V 110 - - ns
V
CC
= 4.5 V 22 - - ns
V
CC
= 6.0 V 19 - - ns
t
h
hold time PE to CP; see Figure 11
V
CC
= 2.0 V 0 - - ns
V
CC
= 4.5 V 0 - - ns
V
CC
= 6.0 V 0 - - ns
TE
to CP; see Figure 12
V
CC
= 2.0 V 0 - - ns
V
CC
= 4.5 V 0 - - ns
V
CC
= 6.0 V 0 - - ns
Pn to CP; see Figure 11
V
CC
= 2.0 V 0 - - ns
V
CC
= 4.5 V 0 - - ns
V
CC
= 6.0 V 0 - - ns
f
max
maximum frequency see Figure 7
V
CC
= 2.0 V 2.0 - - MHz
V
CC
= 4.5 V 10 - - MHz
V
CC
= 6.0 V 12 - - MHz
Table 7. Dynamic characteristics
…continued
GND = 0 V; t
r
=t
f
=6 ns; C
L
= 50 pF; see Figure 13.
Symbol Parameter Conditions Min Typ Max Unit
