74HC40103 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 4 — 27 January 2016 16 of 24
NXP Semiconductors
74HC40103
8-bit synchronous binary down counter
The shaded areas indicate when the input is permitted to
change for predictable output performance.
V
M
= 0.5 V
I
V
M
= 0.5 V
I
Fig 11. Waveforms showing hold and set-up times for
Pn, PE to CP
Fig 12. Waveforms showing hold and set-up times for
MR or PE to CP
9
0
9
0
VWDEOH
DDE
3(LQSXW
&3LQSXW
3WR3
LQSXW
W
VX
W
K
9
0
W
VX
W
K
DDE
7(RU3(
LQSXW
&3LQSXW
9
0
W
VX
W
K
9
0
Test data is given in Table 8.
Definitions for test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= Load capacitance including jig and probe capacitance.
Fig 13. Test circuit for measuring switching times
PQD
9
&&
9
,
9
2
5
7
&
/
38/6(
*(1(5$725
'87
Table 8. Test data
Supply Input Load
V
CC
V
I
t
r
, t
f
C
L
2.0 V V
CC
6 ns 50 pF
4.5 V V
CC
6 ns 50 pF
6.0 V V
CC
6 ns 50 pF
5.0 V V
CC
6 ns 15 pF
