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SL28770ELI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
SL28770
DOC#: SP-AP-0065 (Rev. AA) Page 4 of 22
36:29 Data byte 1–8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
45:38 Data byte 2–8 bits 37:30 Byte Count from slave–8 bits
46 Acknowledge from slave 38 Acknowledge
.... Data Byte /Slave Acknowledges 46:39 Data byte 1 from slave–8 bits
.... Data Byte N–8 bits 47 Acknowledge
.... Acknowledge from slave 55:48 Data byte 2 from slave–8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave / Acknowledge
.... Data Byte N from slave–8 bits
.... NOT Acknowledge
.... Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address–7 bits 8:2 Slave address–7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code–8 bits 18:11 Command Code–8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte–8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address–7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave–8 bits
38 NOT Acknowledge
39 Stop
Table 2. Block Read and Block Write Protocol (continued)
Block Write Protocol Block Read Protocol
Bit Description Bit Description
SL28770
DOC#: SP-AP-0065 (Rev. AA) Page 5 of 22
Control Registers
Byte 0: Control Register 0
Bit @Pup Name Description
7 HW FS CPU Frequency Select Bit, set by HW
0 = 133MHz, 1= 100MHz
6 0 RESERVED RESERVED
5 1 RESERVED RESERVED
4 0 iAMT_EN iAMT Enable
0 = Legacy Mode, 1 = iAMT Enabled
3 0 RESERVED RESERVED
2 0 SRC_Main_SEL Select source for SRC clock
0 = SRC_MAIN = PLL1, PLL3_CFG Table applies
1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply
1 0 SATA_SEL Select source of SATA clock
0 = SATA = SRC_MAIN, 1= SATA = PLL4
0 1 PD_Restore Save configuration when PD# is asserted
0 = Config. cleared, 1 = Config. saved
Byte 1: Control Register 1
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 0 PLL1_SS_DC Select for down or center SS
0 = Down spread, 1 = Center spread
5 0 PLL3_SS_DC Select for down or center SS
0 = Down spread, 1 = Center spread
4 0 PLL3_CFB3 CFB Bit [4:1] only applies when SRC_Main_SEL = 0 (Byte 0, bit 2 =0)
See Table 4 on page 9 for Configuration.
3 0 PLL3_CFB2
2 1 PLL3_CFB1
1 0 PLL3_CFB0
0 1 RESERVED RESERVED
Byte 2: Control Register 2
Bit @Pup Name Description
7 1 REF_OE Output enable for REF
0 = Output Disabled, 1 = Output Enabled
6 1 USB_48_OE Output enable for USB_48
0 = Output Disabled, 1 = Output Enabled
5 1 RESERVED RESERVED
4 1 RESERVED RESERVED
3 1 RESERVED RESERVED
2 1 RESERVED RESERVED
1 1 RESERVED RESERVED
0 1 RESERVED RESERVED
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 1 RESERVED RESERVED
SL28770
DOC#: SP-AP-0065 (Rev. AA) Page 6 of 22
5 1 RESERVED RESERVED
4 1 RESERVED RESERVED
3 1 RESERVED RESERVED
2 1 RESERVED RESERVED
1 1 RESERVED RESERVED
0 1 RESERVED RESERVED
Byte 3: Control Register 3
Byte 4: Control Register 4
Bit @Pup Name Description
7 1 RESERVED RESERVED
6 1 SATA_OE Output enable for SATA
0 = Output Disabled, 1 = Output Enabled
5 1 SRC_OE Output enable for SRC
0 = Output Disabled, 1 = Output Enabled
4 1 DOT96_OE Output enable for DOT96
0 = Output Disabled, 1 = Output Enabled
3 1 CPU1_OE Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
2 1 CPU0_OE Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
1 1 PLL1_SS_EN Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
0 1 PLL3_SS_EN Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
Byte 5: Control Register 5
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 RESERVED RESERVED
5 0 RESERVED RESERVED
4 0 RESERVED RESERVED
3 0 RESERVED RESERVED
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED
0 0 RESERVED RESERVED
Byte 6: Control Register 6
Bit @Pup Name Description
7 0 RESERVED RESERVED
6 0 RESERVED RESERVED
5 0 REF Bit1 REF slew rate control
(see Byte 13 for Slew Rate Bit 0 and Bit 2)
0 = High, 1 = Low
4 0 RESERVED RESERVED
3 0 27MHz Bit 1 27MHz slew rate control
(see Byte 13 for Slew Rate Bit 0 and Bit 2)
0 = High, 1 = Low
2 0 RESERVED RESERVED
1 0 RESERVED RESERVED
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

SL28770ELI

Mfr. #:
Buy SL28770ELI
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products Calpella, IronLake, Jasper Forest, Ibex Peak. Additional USB to 28748
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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