NCP1337
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VCS
rippleOUT
VCS
rippleIN
CS
(envelope)
Min T
ON
CS
Setpoint
VCC
min
VCC
on
VCC
Soft−Skip on
each re−start
Figure 5. Soft−Skip Mode in Standby
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Soxyless
The “Valley point detection” is based on the observation
of the Power MOSFET Drain voltage variations. When the
transformer is fully demagnetized, the Drain voltage
evolution from the plateau level down to the V
IN
asymptote
is governed by the resonating energy transfer between the
L
P
transformer inductor and the global capacitance present
on the Drain. These voltage oscillations create current
oscillation in the parasitic capacitor across the switching
MOSFET (modelized by the Crss capacitance between
Gate and Drain): a negative current (flowing out of DRV
pin) takes place during the decreasing part of the Drain
oscillation, and a positive current (entering into the DRV
pin) during the increasing part.
The Drain valley corresponds to the inversion of the
current (i.e., the zero crossing): by detecting this point, we
always ensure a true valley turn−on.
Lprim
Crss
DRV
Isoxy
Vswitch
T
SWING
t
Figure 6. Soxyless Concept
The current in the Power MOSFET gate is:
Igate = Vringing/Zc (with Zc the capacitance impedance)
so
Igate = Vringing S (2 S p S Fres S Crss)
The magnitude of this gate current depends on the
MOSFET, the resonating frequency and the voltage swing
present on the Drain at the end of the plateau voltage.
The dead time T
SWING
is given by the equation:
Tswing + 0.5ńFres + p *Lp*Cdrain
Ǹ (eq. 1)
(where L
P
is the primary transformer inductance and
C
DRAIN
the total capacitance present on the MOSFET
Drain. This capacitance includes the snubber capacitor if
any, the transformer windings stray capacitance plus the
parasitic MOSFET capacitances C
OSS
and C
RSS
).
Internal Feedback Circuitry
To simplify the implementation of a primary regulation,
it is necessary to inject a current into the FB pin (instead of
sourcing it out). But to have a precise primary regulation,
the voltage present on FB pin must be regulated. Figure 8
gives the FB pin internal implementation: the circuitry
combines the functions of a current to voltage converter
and a voltage regulator.
FB
+
-
+
3 V
Vdd
Internal
Setpoint
20 kHz
Low−pass Filter
Figure 7. Internal Implementation of FB Pin
NCP1337
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The input information is the current injected in FB pin by
the feedback loop. The range of current is from 40 mA for
overload detection to 220 mA corresponding to V
CSrippleIN
.
In transients, currents from 0 to more than 400 mA may also
appear: the circuitry is able to sustain them.
To regulate the FB pin voltage, the operational amplifier
needs to have a high gain and a wide bandwidth. But the
feedback information used internally needs to be filtered,
because we don’t want the controller to be sensitive to the
switching noise. For this purpose, a 20 kHz filter is added
after the shunt regulator, and any reading of the feedback
signal (for ripple mode, fault detection, or setpoint
elaboration) is done after.
Soft Burst Mode (Protection Mode)
The NCP1337 features a fault timer to detect an overload
completely independently of the V
CC
voltage. As soon as
the feedback loop asks for the maximum power, a fault is
detected, and an internal timer is started. When the fault
disappears the timer is reset, but if the timer reaches 80 ms,
the protection mode is activated.
Once this protection is toggled, output pulses are stopped
and DSS is deactivated (HV current source turn−on
threshold changes from VCC
MIN
to VCC
LATCH
). V
CC
slowly decreases (the current consumption is ICC3), and
the HV current source is switched ON when V
CC
reaches
VCC
LATCH
. As a result V
CC
increases until VCC
ON
, but the
controller does not start as the output is still forced low.
V
CC
decreases again down to VCC
LATCH
, and a new
start−up cycle occurs. On the second attempt, the output is
released, and NCP1337 effectively starts, with the
soft−start activated. Figure 4 illustrates this behavior.
Safety Features
The NCP1337 includes several safety features to help the
power supply designer to build a rugged design:
OVP (Overvoltage on V
CC
): Activated when voltage
on pin V
CC
is higher than 18.6 V
Brown−Out (Undervoltage lockout on bulk voltage):
Activated when voltage on pin BO is below 500 mV
Disable (Comparator activated by an external signal):
Activated when the voltage on BO pin is higher than
3.0 V but below 5.0 V
TSD (Temperature shutdown): Typically activated
when the die temperature is above 150°C, released at
120°C
All these events have the same consequence for the
controller: the DRV pulses are stopped. When the condition
disappears, the controller restarts with the soft−start
activated. However, as the fault timer is still active, it can
time out while the switching is stopped. As a result the
controller will go into protection mode, and won’t restart
instantaneously.
Permanent Latch (Comparator activated by an external
signal): Activated when the voltage on BO pin is
above 5.0 V
When this comparator is activated, the DRV pulses are
stopped, and the DSS is deactivated (only the start−up
current source is turned on each time V
CC
reaches
VCC
LATCH
, maintaining V
CC
between 5.0 V and 12 V):
the controller stays in this position until the V
CC
voltage is
decreased below 4.0 V, i.e., when the power supply is
unplugged from the mains (in normal operation, as soon as
a voltage is present on the HV pin, V
CC
is always kept
above 5.0 V).
Soft−Skip Mode
The soft ripple mode is a skip mode with a large
hysteresis on the skip comparator in order to ensure a
noise−free and high−efficiency operation in low−load
conditions (standby). When internal setpoint is reaching
V
CSrippleIN
= 100 mV (corresponding to 20% of the
maximum setpoint), the output pulses are stopped. Then
FB loop asks for more power and internal setpoint is
increasing: when it reaches V
CSrippleOUT
= 130 mV
(corresponding to 25% of the maximum setpoint), the
output starts switching again. Soft−Skip is activated in each
activity following a stop period. See Figure 5 for detailed
timing diagram.
HV Current Source
NCP1337 features a DSS, to allow operation without any
auxiliary voltage. But to protect the die in case of
short−circuit on V
CC
pin, the current delivered by the HV
current source is lowered when V
CC
voltage is below 1.5 V.
In the case the current consumed on the DRV pin is
higher than the DSS capability (high Qg MOSFET or
failure), the HV current source is switched ON when V
CC
reaches VCC
MIN
, but the voltage on V
CC
pin keep on
decreasing. If there is no UVLO threshold to stop the DRV
pulses, the gate voltage will become too low and the risk is
high to destroy the MOSFET. NCP1337 features an
additional comparator, which threshold is 9.0 V: when V
CC
reaches this level whereas the HV current source is ON,
DRV pulses are stopped and the protection mode is
activated.
The maximum dV/dt that can be applied to the VCC pin
is 9.0 V/ms. The supply capacitor is selected to ensure the
maximum dV/dt is not exceeded.

NCP1337DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers PWM CONTROLLER
Lifecycle:
New from this manufacturer.
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