ICS853S014AGI REVISION D MAY 23, 2013 2 ©2013 Integrated Device Technology, Inc.
ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Pin Description and Pin Characteristic Table
Table 1. Pin Descriptions
NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2
Q0, nQ0
Output Differential output pair. LVPECL/ECL interface levels.
3, 4
Q1, nQ1
Output Differential output pair. LVPECL/ECL interface levels.
5, 6
Q2, nQ2
Output Differential output pair. LVPECL/ECL interface levels.
7, 8
Q3, nQ3
Output Differential output pair. LVPECL/ECL interface levels.
9, 10
Q4, nQ4
Output Differential output pair. LVPECL/ECL interface levels.
11 V
EE
Power Negative supply pin.
12 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects
PCLK0, nPCLK0 inputs. Single-ended LVPECL interface levels.
13 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input.
14 nPCLK0 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
15 V
BB
Output Bias voltage.
16 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input.
17 nPCLK1 Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
18, 20 V
CC
Power Positive supply pins.
19
nEN
Input Pulldown
Synchronizing clock enable. When LOW, clock outputs follow clock input. When
HIGH, Qx outputs are forced low, nQx outputs are forced high.
Single-ended LVPECL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
R
PULLDOWN
Input Pulldown Resistor 37 k
R
VCC/2
Pullup/Pulldown Resistors 37 k
