ICS853S014AGI REVISION D MAY 23, 2013 7 ©2013 Integrated Device Technology, Inc.
ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
AC Electrical Characteristics
Table 5. AC Characteristics, V
CC
= -3.8V to -2.375V or , V
CC
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C
NOTE: All parameters are measured at f 1GHz, unless otherwise noted.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter
-40°C 25°C 85°C
UnitsMin Typ Max Min Typ Max Min Typ Max
f
MAX
Output Frequency 2 2 2 GHz
t
PD
Propagation Delay; NOTE 1 250 425 300 450 350 500 ps
tjit
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section (ƒ = 156.25MHz,
12kHz - 20MHz)
0.06 0.10 0.07 0.10 0.08 0.10 ps
tsk(o) Output Skew; NOTE 2, 4 55 55 55 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 100 100 ps
t
R
/ t
F
Output
Rise/Fall Time
20% to 80% 70 220 80 220 90 220 ps
t
S
Clock Enable Setup Time 100 50 100 50 100 50 ps
t
H
Clock Enable Hold Time 200 140 200 140 200 140 ps
ICS853S014AGI REVISION D MAY 23, 2013 8 ©2013 Integrated Device Technology, Inc.
ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "IFR2042 10kHz – 5.4GHz Low Noise Signal
Generator used as external input to an Agilent 8133A 3GHz Pulse
Generator".
Additive Phase Jitter @ 156.25MHz
12kHz to 20MHz = 0.07ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
ICS853S014AGI REVISION D MAY 23, 2013 9 ©2013 Integrated Device Technology, Inc.
ICS853S014I Data Sheet LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Parameter Measurement Information
LVPECL Output Load Test Circuit
Part-to-Part Skew
Output Rise/Fall Time
Differential Input Level
Output Skew
Propagation Delay
SCOPE
Qx
nQx
V
EE
V
CC
2V
-1.8V to -0.375V
tsk(pp)
Part 1
Part 2
nQx
Qx
nQy
Qy
20%
80%
80%
20%
t
R
t
F
V
SWING
nQ0:nQ4
Q0:Q4
V
CC
V
EE
V
CMR
Cross Points
V
PP
nPCLKx
PCLKx
tsk(o)
nQx
Qx
nQy
Qy
t
PD
nQ0:nQ4
Q0:Q4
nPCLKx
PCLKx

853S014AGILFT

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IDT
Description:
Clock Drivers & Distribution SMALL SIGE ARRAY
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