LT3645
18
3645f
APPLICATIONS INFORMATION
P1 has a fi nite on-resistance which will result in power
dissipation and some loss in effi ciency. For higher buck
output voltage applications, a smaller PFET may be used
since the gate drive will be higher.
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 13 shows the
recommended component placement with trace, ground
plane, and via locations.
Note tha t lar ge, swi tche d cur re nt s fl ow in the LT3645’s V
IN
and SW pins, the catch diode (D1), and the input capacitor
(C1). The loop formed by these components should be as
small as possible and tied to system ground in only one
place. These components, along with the inductor and
output capacitor, should be placed on the same side of the
circuit board, and their connections should be made on
that layer. Place a local, unbroken ground system ground in
only one place. These components, along with the inductor
and output capacitor, should be placed on the same side
of the circuit board, and their connections should be made
on that layer. Place a local, unbroken ground plane below
these components, and tie this ground plane to system
ground at one location (ideally at the ground terminal of
the output capacitor C1). The SW and BOOST nodes should
be kept as small as possible. Finally, keep the FB nodes
small so that the ground pin and ground traces will shield
them from the SW and BOOST nodes. Include vias near
the exposed GND pad of the LT3645 to help remove heat
from the LT3645 to the ground plane.
High Temperature Considerations
The die temperature of the LT3645 must be lower than
the maximum rating of 125°C (150°C for H-grade). This
is generally not a concern unless the ambient tempera-
ture is above 85°C. For higher temperatures, extra care
should be taken in the layout of the circuit to ensure good
heat sinking at the LT3645. The maximum load current
should be derated as the ambient temperature approaches
125°C. The die temperature is calculated by multiplying the
LT3645 power dissipation by the thermal resistance from
junction to ambient. Power dissipation within the LT3645
can be estimated by calculating the total power loss from
an effi ciency measurement and subtracting the catch diode
loss. The resulting temperature rise at full load is nearly
independent of input voltage. Thermal resistance depends
upon the layout of the circuit board, but 68°C/W is typical
for the QFN (UD) package, and 40°C/W is typical for the
MSE package. Thermal shutdown will turn off the Buck
and LDO when the die temperature exceeds 160°C, but
it is not a warrant to allow operation at die temperatures
exceeding 125°C (150°C for H-grade).
Other Linear Technology Publications
Application Notes 19, 35, and 44 contain more detailed
descriptions and design information for step-down regu-
lators and other switching regulators. The LT1376 data
sheet has an extensive discussion of output ripple, loop
compensation, and stability testing. Design Note 318
shows how to generate a bipolar output supply using a
step-down regulator.
Figure 13.
3645 F13
C3
C2
D1
DA
L1
SW
C4
C1
C5
R1 R3
MAIN PCB
BOARD
POWER
R2
FB1
BOOST
FB2
R4
OUT1
V
IN
V
IN
V
CC2
EN/UVLO
NPG EN2
OUT2
VIA TO LOCAL GROUND PLANE
OUTLINE OF LOCAL GROUND PLANE
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