LT3645
7
3645f
PIN FUNCTIONS
EN/UVLO (Pin 1/Pin 5): The EN/UVLO pin is used to enable
the buck switching regulator and the low dropout linear
regulator (LDO). An accurate threshold of 1.23V allows the
user to set the undervoltage lockout point with a simple
resistor divider, see Precision Undervoltage Lockout sec-
tion for more information. The EN/UVLO pin can be tied
directly to V
IN
if the UVLO or shutdown is not used.
FB (Pin 2/Pin 6): The FB pin programs the buck output
voltage. The LT3645 regulates the FB pin to 0.8V. The
feedback resistor divider tap should be connected to this
pin. The output voltage is programmed according to the
following equation:
R1= R2 •
V
OUT
0.8
–1
where R1 connects between OUT and FB and R2 connects
between FB and GND. A good value for R2 is 10k.
GND (Pin 3, Exposed Pad Pin 13/Pin 7, Exposed Pad Pin 17):
The GND pin should be tied to a local ground plane below the
LT3645 and the circuit components. Return the feedback
dividers from FB and FB2 to this pin. The exposed pad
must be soldered to the PCB and electrically connected
to ground. Use a large ground plane and thermal vias to
optimize thermal performance.
DA (Pin 4/Pin 8): The DA pin senses the external catch
diode current and prevents the buck regulator from switch-
ing if the sensed current is too high. Connect the anode
of the external Schottky catch diode to this pin.
BOOST (Pin 5/Pin 10): The BOOST pin provides a drive
voltage to the internal bipolar NPN power switch. Tie a
0.1µF capacitor between the BOOST and SW pins.
SW (Pin 6/Pin 9): The SW pin is the output of the internal
buck power switch. Connect the inductor and the cathode
of the external catch Schottky diode to this pin.
V
IN
(Pin 7/ Pin 11): The V
IN
pin supplies current to the
LT3645s internal circuitry, to the internal buck power
switch, and to the LDO. The V
IN
pin must be locally
bypassed.
V
CC2
(Pin 8/Pin 14): The V
CC2
pin supplies current to the
linear regulator’s output device. The V
CC2
pin is also the
anode of an internal Schottky diode used to generate the
BOOST voltage. The V
CC2
pin must be tied to a voltage
source greater than 2.5V to utilize the internal Schottky
boost diode. If the V
CC2
pin is tied to a voltage lower than
2.5V, then an external Schottky diode must be connected
between a power supply greater than 2.5V (anode) and
the BOOST pin (cathode). Bypass this pin to ground with
a 0.1µF capacitor close to the part.
OUT2 (Pin 9/Pin 15): The OUT2 pin is the output of the
LDO. Connect a capacitor of at least 0.47µF from this pin
to ground. See Frequency Compensation (LDO) section
for more details.
FB2 (Pin 10/Pin 16): The FB2 pin programs the LDO output
voltage. The LT3645 regulates the FB2 pin to 0.797V. The
feedback resistor divider tap should be connected to this
pin. The output voltage is programmed according to the
following equation:
R3 = R4 t
V
OUT2
0.797
–1
where R3 connects between OUT2 and FB2 and R4
connects between FB2 and GND. A good value for R4 is
10k.
EN2 (Pin 11/Pin 4): The EN2 pin is used to enable the linear
regulator. Pull this pin above 1.6V to enable the LDO. Pull
EN2 below 0.5V to disable the LDO.
NPG (Pin 12/Pin 3): The NPG pin is an open-collector
output used to indicate that both buck and LDO output
voltages are in regulation. The NPG pin pulls low when
FB and FB2 both exceed 720mV.
NC (Pins 1, 2, 12, 13, QFN Only): No Connect Pins. Tie
these to ground.
(MSOP/QFN)
LT3645
8
3645f
BLOCK DIAGRAM
V
IN
EN/UVLO
START
1.23V
1.3V
START
BUCK
START
LDO
ERROR
AMP
CURRENT
COMPARATOR
V
C
BUCK
DRIVER
LOGIC
–40mV
BOOST
0.8V
REFERENCE
PGOOD
C1
EN2
NPG
GND
+
+
+
+
+
+
OSCILLATOR
SOFT-START
SQ
R
+
Q1
SW
DA
GND
C2
L1
D1
R1
R2
C4 R3
R4
C3
FB
V
CC2
V
IN
OUT2
LDO DRIVER
ERROR
AMP
0.797V
0.72V
FB2
Q2
SOFT-START
+
+
LDO ON
ON OFF
SLOPE COMPENSATION
LT3645
9
3645f
OPERATION
The LT3645 includes a constant frequency, current mode
step-down buck switching regulator together with a low-
dropout regulator (LDO).
If EN/UVLO is less than ~0.7V, both the buck and LDO
are off, the output is disconnected and the input current
is less than 2A. The buck turns on when EN/UVLO is
greater than 1.23V. An undervoltage lockout (UVLO)
turns the buck and LDO off when V
IN
is less than 3.4V.
An overvoltage lockout (OVLO) turns the buck and LDO
off when V
IN
is greater than 38.5V. The par t will withstand
nonrepetitive one second input voltage transients up to
55V. An internal thermal shutdown circuit monitors the die
temperature and shuts both the buck and LDO off if the
die temperature exceeds ~160°C. The thermal shutdown
has 10 degrees of hysteresis.
An internal regulator provides power to the control circuitry
and produces the 0.8V feedback voltage for the buck and
LDO error amplifi ers.
An internal, fi xed-frequency oscillator in the step-down
regulator enables an RS flip-flop, turning on the internal
power switch Q1. A comparator monitors the current
flowing between the V
IN
and SW pins, turning the switch
off when this current reaches a level determined by the
voltage at V
C
and the internal slope-compensation. An error
amplifier servos the V
C
node. The output of an external
resistor divider between OUT and ground is tied to the
V
FB
pin and presented to the negative error amp input.
The positive input to the error amp is a 0.8V reference, so
the voltage loop forces the V
FB
pin to 0.8V. The reference
voltage of the buck error amplifi er is ramped over 900µs
during the soft-start period. When V
C
rises, it results in an
increase in output current, and when V
C
falls, it results in
less output current. Current limit is provided by an active
clamp on the V
C
node.
The buck power switch (Q1) is driven from the BOOST
pin. An external capacitor and internal diode are used to
generate a voltage at the BOOST pin that is higher than the
input supply, which allows the driver to fully saturate the
internal bipolar NPN power switch for ef cient operation.
An external diode can be used to make the BOOST drive
more effective at low output voltages.
The oscillator reduces the LT3645’s operating frequency
during the soft-start period. This frequency foldback helps
to control the output current during startup.
The current in the external catch diode (D1) is sensed
through the DA pin. If the catch diode current exceeds
0.9A, the oscillator frequency is decreased. This prevents
current runaway during startup or overload.
The LDO only operates if EN/UVLO is greater than 1.23V
and EN2 is greater than 1.3V. If EN/UVLO is low and EN2
is high, the LDO will not start. When EN2 > 1.3V and EN/
UVLO > 1.23V, the LDO power transistor will turn on and
regulate the output at the OUT2 pin. An error amplifi er
driving Q2 has its positive input at the 0.797V reference.
The output of an external resistor divider between OUT2
and ground is tied to the V
FB2
pin and presented to the
negative error amp input, forcing the V
FB2
pin to 0.797V.
The reference voltage of the LDO error amplifi er is ramped
over 600µs during the soft-start period. The LDO power
transistor (Q2) is driven from the V
IN
pin. Q2 is a bipolar
NPN which draws its collector current from the V
CC2
pin.
The NPG pin is an open-collector output that indicates
when both buck and LDO outputs are in at least 90% in
regulation. When FB and FB2 rise above 720mV, the NPG
pin is pulled low.

LT3645IMSE#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 36Vin (55V Trans) 500mA Buck plus 200mA LDO
Lifecycle:
New from this manufacturer.
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