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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
www.fairchildsemi.com
FM27C512 Rev. A
Capacitance T
A
= +25°C, f = 1 MHz (Note 2)
Symbol Parameter Conditions Typ Max Units
C
IN1
Input Capacitance V
IN
= 0V 6 12 pF
except OE/V
PP
C
OUT
Output Capacitance V
OUT
= 0V 9 12 pF
C
IN2
OE/V
PP
Input V
IN
= 0V 20 25 pF
Capacitance
AC Test Conditions
Output Load 1 TTL Gate and C
L
= 100 pF (Note 8)
Input Rise and Fall Times ≤5 ns
Input Pulse Levels 0.45V to 2.4V
Timing Measurement Reference Level (Note 9)
Inputs 0.8V and 2V
Outputs 0.8V and 2V
AC Waveforms (Notes 6, 7)
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note 2: This parameter is only sampled and is not 100% tested.
Note 3: OE may be delayed up to t
ACC
–t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4: The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5: TRI-STATE may be attained using OE or CE .
Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device
between V
CC
and GND.
Note 7: The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8: 1 TTL Gate: I
OL
= 1.6 mA, I
OH
= -400 µA. C
L
: 100 pF includes fixture capacitance.
Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Address Valid
Valid Output
Hi-Z
2V
0.8V
2V
0.8V
2V
0.8V
ADDRESS
OUTPUT
CE
OE
t
CE
2V
0.8V
(Note 3)
(Note 3)
t
DF
(Note 4, 5)
(Note 4, 5)
t
OH
Hi-Z
t
OE
ACC
t
CF
t
DS800035-4
