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NCV85081BDS50G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
NCV8508B
http://onsemi.com
10
CIRCUIT DESCRIPTION
Functional Description
To reduce the drain on the battery, a system can go into a
low current consumption mode whenever it is not
performing a main routine. The Wakeup signal is generated
continuously and is used to interrupt a microcontroller that
is in sleep mode. The nominal output is a 5.0 (or 3.3 V) volt
square wave (voltage generated from V
OUT
) with a duty
cycle of 50% at a frequency that is determined by a timing
resistor, R
Delay
.
When the microprocessor receives a rising edge from the
Wakeup output, it must issue a Watchdog pulse and check its
inputs to decide if it should resume normal operations or
remain in the sleep mode.
The first falling edge of the Watchdog signal causes the
Wakeup to go low within 2.0 ms (typ) and remain low until
the next Wakeup cycle (see Figure 18). Other Watchdog
pulses received within the same cycle are ignored (Figure 3).
During power up, RESET
is held low until the output
voltage is in regulation. During operation, if the output
voltage shifts below the regulation limits, the RESET
toggles low and remains low until proper output voltage
regulation is restored. After the RESET
delay, RESET
returns high.
The Watchdog circuitry continuously monitors the input
Watchdog signal (WDI) from the microprocessor. The
absence of a falling edge on the Watchdog input during one
Wakeup cycle will cause a RESET
pulse to occur at the end
of the Wakeup cycle. (see Figure 4).
The Wakeup output is pulled low during a RESET
regardless of the cause of the RESET. After the RESET
returns high, the Wakeup cycle begins again (see Figure 4).
The RESET
Delay Time, Wakeup signal frequency and
RESET
high to Wakeup delay time are all set by one external
resistor R
Delay
.
Wakeup Period = (4.17 × 10
−7
)R
Delay
RESET Delay Time = (5.21 × 10
−8
)R
Delay
RESET HIGH to Wakeup Delay Time = (2.08 × 10
−7
)R
Delay
Resistor temperature coefficient and tolerance as well as
the tolerance of the NCV8508B must be taken into account
in order to get the correct system tolerance for each
parameter.
Figure 18. Wakeup Response to WDI
Wakeup
WDI
Wakeup
Response
to WDI
Figure 19. Wakeup Response to RESET (Low
Voltage)
Wakeup
Response
to RESET
RESET
Wakeup
NCV8508B
http://onsemi.com
11
Recommend Thermal Data for D
2
PAK−7 Package
Parameter Test Conditions Typical Value Units
min−pad board (Note 5) 1”−pad board (Note 6)
Junction−to−Lead (psi−JL, Y
JL
)
12 12 °C/W
Junction−to−Ambient (R
q
JA
, q
JA
)
84 48 °C/W
5. 1 oz. copper, 118 mm
2
copper area, 0.062” thick FR4.
6. 1 oz. copper, 626 mm
2
copper area, 0.062” thick FR4.
Package construction
With and without mold compound
Various copper areas used
for heat spreading
Active Area (red) times 2
(only showing 1/2 symmetry)
Figure 20. PCB Layout and Package Construction for Simulation
NCV8508B
http://onsemi.com
12
Table 1. D
2
PAK 7−Lead Thermal RC Network Models
118 mm
2
626 mm
2
118 mm
2
626 mm
2
Cu Area
Cauer Network Foster Network
C’s C’s Units Tau Tau units
1 8.6E−07 8.6E−07 W−s/C 1.00E−07 1.00E−07 sec
2 3.6E−06 3.6E−06 W−s/C 1.00E−06 1.00E−06 sec
3 1.4E−05 1.4E−05 W−s/C 1.00E−05 1.00E−05 sec
4 1.4E−04 1.4E−04 W−s/C 3.07E−04 3.07E−04 sec
5 6.4E−04 6.4E−04 W−s/C 1.00E−03 1.00E−03 sec
6 1.1E−02 1.1E−02 W−s/C 6.00E−03 6.00E−03 sec
7 3.0E−02 3.0E−02 W−s/C 2.00E−02 2.00E−02 sec
8 4.9E−01 5.2E−01 W−s/C 1.43E+00 1.43E+00 sec
9 4.8E−01 1.5E+00 W−s/C 6.15E+00 3.82E+00 sec
10 6.9E−01 9.5E−01 W−s/C 1.04E+02 9.68E+01 sec
R’s R’s R’s R’s
1 0.147 0.147 C/W 0.090 0.090 C/W
2 0.301 0.301 C/W 0.194 0.194 C/W
3 0.603 0.603 C/W 0.614 0.614 C/W
4 2.733 2.733 C/W 1.200 1.200 C/W
5 1.178 1.178 C/W 2.600 2.600 C/W
6 1.369 1.366 C/W 0.100 0.100 C/W
7 0.272 0.270 C/W 1.700 1.700 C/W
8 14.820 7.855 C/W 0.100 0.100 C/W
9 6.055 2.741 C/W 6.944 5.181 C/W
10 56.834 30.488 C/W 70.770 35.902 C/W
NOTE: Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in
the Foster network are computed by the square root of time constant R(t) = 166 * sqrt(time(sec)). The constant is derived based
on the active area of the device with silicon and epoxy at the interface of the heat generation.
The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior
due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear
a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily
implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical
tools (for instance, in a spreadsheet program), according to the following formula:
R(t) +
n
S
i + 1
R
i
ǒ
1−e
−tńtau
i
Ǔ
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

NCV85081BDS50G

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Buy NCV85081BDS50G
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators 250 MA, 5 V, LDO
Lifecycle:
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