4
FN2979.3
August 13, 2015
transfer. These two signals usually go to the chip select and
direction pins of a transceiver.
The MCE/PDEN
pin changes function with the two modes of
the 82C88. When the 82C88 is in the IOB mode (IOB HIGH),
the PDEN
signal serves as a dedicated data enable signal
for the I/O or Peripheral System bus.
Interrupt Acknowledge and MCE
The MCE signal is used during an interrupt acknowledge
cycle if the 82C88 is in the System Bus mode (IOB LOW).
During any interrupt sequence, there are two interrupt
acknowledge cycles that occur back to back. During the first
interrupt cycle no data or address transfers take place. Logic
should be provided to mask off MCE during this cycle. Just
before the second cycle begins the MCE signal gates a
master Priority Interrupt Controller’s (PIC) cascade address
onto the processors local bus where ALE (Address Latch
Enable) strobes it into the address latches. On the leading
edge of the second interrupt cycle, the addressed slave PIC
gates an interrupt vector onto the system data bus where it is
read by the processor.
If the system contains only one PIC, the MCE signal is not
used. In this case, the second Interrupt Acknowledge signal
gates the interrupt vector onto the processor bus.
Address Latch Enable and Halt
Address Latch Enable (ALE) occurs during each machine
cycle and serves to strobe the current address into the
82C82/82C83H address latches. ALE also serves to strobe
the status (S0
, S1, S2) into a latch for halt state decoding.
Command Enable
The Command Enable (CEN) input acts as a command
qualifier for the 82C88. If the CEN pin is high, the 82C88
functions normally. If the CEN pin is pulled LOW, all
command lines are held in their inactive state (not three-
state). This feature can be used to implement memory
partitioning and to eliminate address conflicts between
system bus devices and resident bus devices.
82C8882C88
5
FN2979.3
August 13, 2015
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
M82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
CERDIP Package. . . . . . . . . . . . . . . . 75 18
CLCC Package . . . . . . . . . . . . . . . . . 85 22
PDIP Package . . . . . . . . . . . . . . . . . . 75 N/A
PLCC Package. . . . . . . . . . . . . . . . . . 75 N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(PLCC - Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications V
CC
= 5.0V 10%;
T
A
= 0°C to +70°C (C82C88);
T
A
= -40°C to +85°C (I82C88);
T
A
= -55°C to +125°C (M82C88)
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
V
IH
Logical One Input Voltage 2.0
2.2
-
-
V
V
C82C88, I82C88
M82C88
V
IL
Logical Zero Input Voltage - 0.8 V
VIHC CLK Logical One Input Voltage V
CC
-0.8 - V
VILC CLK Logical Zero Input Voltage - 0.8 V
V
OH
Output High Voltage
Command Outputs
3.0
V
CC
-0.4
-V
V
I
OH
= -8.0mA
I
OH
= -2.5mA
Output High Voltage
Control Outputs
3.0
V
CC
-0.4
-V
V
I
OH
= -4.0mA
I
OH
= -2.5mA
V
OL
Output Low Voltage
Command Outputs
-0.5VI
OL
= +12.0mA
Output Low Voltage
Control Outputs
-0.4VI
OL
= +8.0mA
I
I
Input Leakage Current -1.0 1.0 AV
IN
= GND or V
CC
, except S0, S1, S2,
DIP Pins 1-2, 6, 15
IBHH Input Leakage Current-Status Bus -50 -300 AV
IN
= 2.0V, S0, S1, S2 (See Note 1)
IO Output Leakage Current -10.0 10.0 AV
O
= GND or V
CC
, IOB = GND, AEN = V
CC
,
DIP Pins 7-9, 11-14
ICCSB Standby Power Supply - 10 AV
CC
= 5.5V, V
IN
= V
CC
or GND, Outputs Open
ICCOP Operating Power Supply Current - 1 mA/MHz V
CC
= 5.5V, Outputs Open (See Note 2)
NOTES:
1. IBHH should be measured after raising the V
IN
on S0, S1, S2 to V
CC
and then lowering to valid input high level of 2.0V.
2. ICCOP = 1mA/MHz of CLK cycle time (TCLCL)
Capacitance T
A
= +25°C
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
CIN Input Capacitance 10 pF FREQ = 1MHz, all measurements are
referenced to device GND
COUT Output Capacitance 17 pF
82C8882C88
6
FN2979.3
August 13, 2015
AC Electrical Specifications V
CC
= 5.0V 10%;
T
A
= 0°C to +70°C (C82C88);
T
A
= -40°C to +85°C (I82C88);
T
A
= -55°C to +125°C (M82C88)
SYMBOL PARAMETER
8MHz 10MHz 12MHz
UNITS
TEST
CONDITIONSMIN MAX MIN MAX MIN MAX
TIMING REQUIREMENTS
(1) TCLCL CLK Cycle Period 125 - 100 - 83 - ns
(2) TCLCH CLK Low Time 55 - 50 - 34 - ns
(3) TCHCL CLK High Time 40 - 37 - 34 - ns
(4) TSVCH Status Active Setup Time 35 - 35 - 35 - ns
(5) TCHSV Status Inactive Hold Time 10 - 10 - 5 - ns
(6) TSHCL Status Inactive Setup Time 35 - 35 - 35 - ns
(7) TCLSH Status Active Hold Time 10 - 10 - 5 - ns
TIMING RESPONSES
(8) TCVNV Control Active Delay 5 45 5 45 5 45 ns 1
(9) TCVNX Control Inactive Delay 10 45 10 45 10 35 ns 1
(10) TCLLH ALE Active Delay (from CLK) - 20 - 20 - 20 ns 1
(11) TCLMCH MCE Active Delay (from CLK) - 25 - 23 - 23 ns 1
(12) TSVLH ALE Active Delay (from Status) - 20 - 20 - 20 ns 1
(13) TSVMCH MCE Active Delay (from Status) - 30 - 23 - 23 ns 1
(14) TCHLL ALE Inactive Delay 4 18 4 18 4 18 ns 1
(15) TCLML Command Active Delay 5 35 5 35 5 35 ns 2
(16) TCLMH Command Inactive Delay 5 35 5 35 5 35 ns 2
(17) TCHDTL Direction Control Active Delay - 50 - 50 - 50 ns 1
(18) TCHDTH Direction Control Inactive Delay - 30 - 30 - 30 ns 1
(19) TAELCH Command Enable Time (Note 1) - 40 - 40 - 40 ns 3
(20) TAEHCZ Command Disable Time
(Note 2)
-40-40-40ns 4
(21) TAELCV Enable Delay Time 110 250 110 250 110 250 ns 2
(22) TAEVNV AEN
to DEN - 25 - 25 - 25 ns 1
(23) TCEVNV CEN to DEN, PDEN -25-25-25ns 1
(24) TCELRH CEN to Command - TCLML
+10
-TCLML-TCLMLns 2
(25) TLHLL ALE High Time TCLCH -
10
- TCLCH -
10
- TCLCH -
10
nns 1
NOTES:
1. TAELCH measurement is between 1.5V and 2.5V.
2. TAEHCZ measured at 0.5V change in VOUT.
82C8882C88

CP82C88

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
I/O Controller Interface IC 20 0+70C 5 0V 8 0MHZ BUS CNTRLR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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