7
FN2979.3
August 13, 2015
AC Testing Input, Output Waveform
A.C. Testing: All input signals (other than CLK) must switch
between V
IL
-0.4V and V
IH
+0.4. CLK must switch between 0.4V
and V
CC
-0.4V. Input rise and fall times are driven at 1ns/V.
A.C. Test Circuit
TABLE 2. TEST CONDITION DEFINITION TABLE
TEST CONDITION V1 R1 C1
1 2.13V 220 80pF
2 2.29V 91 300pF
3 1.5V 187 300pF
4 1.5V 187 50pF
1.5V 1.5V
V
IL
-0.4V
INPUT
V
IH
+0.4V
V
OL
OUTPUT
V
OH
TEST
POINT
V1
C1 (SEE NOTE)
R1
OUTPUT FROM
DEVICE
UNDER TEST
NOTE:
INCLUDES STRAY AND JIG CAPACITANCE
82C8882C88
8
FN2979.3
August 13, 2015
Timing Waveforms (Note 3)
NOTES:
1. Address/Data Bus is shown only for reference purposes.
2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last.
3. All timing measurements are made at 1.5V unless otherwise specified.
FIGURE 1.
STATE
CLK
S2
, S1, S0
ADDRESS/DATA
ALE
MRDC
, IORC, INTA,
AMWC
, AIOWC
MWTC, IOWC
DEN (READ)
(INTA)
PDEN
(READ)
(INTA)
DEN (WRITE)
PDEN (WRITE)
DT/R
(READ)
(INTA)
MCE
T
4
T
1
T
2
T
3
T
4
TCLCL
(1)
TCLCH
(2)
TCHCL
(3)
TCLSH
(7)
TSHCL
(6)
TSVCH
(4)
TCHSV
(5)
TCLLH
(10)
TSVLH (12)
TCHLL (14)
TCLML
(15)
TCLML
(15)
TCLMH
(16)
TCVNX
(9)
TCVNV
(8)
TCVNV
(8)
TCVNX
(9)
TCHDTH
(18)
TCHDTL
(17)
TCHDTH
(18)
TCLMCH
(11)
TSVMCH
(13)
TCVNX
(9)
2
2
1
WRITE
DATA VALID
ADDRESS
VALID
82C8882C88
9
FN2979.3
August 13, 2015
FIGURE 2. DEN, PDEN QUALIFICATION TIMING
FIGURE 3. ADDRESS ENABLE (AEN
) TIMING (THREE-STATE ENABLE/DISABLE)
NOTES:
1. Address/Data Bus is shown only for reference purposes.
2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last.
3. All timing measurements are made at 1.5V unless otherwise specified.
Timing Waveforms (Note 3) (Continued)
TAEVNV (22)
TCEVNV (23)
CEN
DEN
AEN
PDEN
CEN
TAE LCV
(21)
1.5V
TAELCH (19)
VOH
TCELRH
(24)
TCELRH (24)
TAEHCZ (20)
1.5V
0.5V VOH
OUTPUT
COMMAND
AEN
CEN MUST BE LOW OR INVALID PRIOR TO T2 TO PREVENT THE COMMAND FROM BEING GENERATED.
82C8882C88

CP82C88

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
I/O Controller Interface IC 20 0+70C 5 0V 8 0MHZ BUS CNTRLR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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